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SN74AHCT08QDRQ1

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Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74AHCT08QDRQ1

Texas Instruments · Logic Gates · SOIC-14

SN74AHCT08QDRQ1 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 input A; TTL-compatible input that is overvoltage tolerant up to 5.5 V at any valid VCC, and high impedance when VCC = 0 V.
2 1B input Gate 1 input B; TTL-compatible input that is overvoltage tolerant up to 5.5 V at any valid VCC, and unused inputs must be held at VCC or GND.
3 1Y output Gate 1 output Y; low-drive CMOS output that should not exceed 25 mA load current and should not be pulled above VCC.
4 2A input Gate 2 input A; TTL-compatible input that is overvoltage tolerant up to 5.5 V at any valid VCC, and high impedance when VCC = 0 V.
5 2B input Gate 2 input B; TTL-compatible input that is overvoltage tolerant up to 5.5 V at any valid VCC, and unused inputs must be held at VCC or GND.
6 2Y output Gate 2 output Y; low-drive CMOS output that should not exceed 25 mA load current and should not be pulled above VCC.
7 GND power_in Ground reference pin for the device.
8 3Y output Gate 3 output Y; low-drive CMOS output that should not exceed 25 mA load current and should not be pulled above VCC.
9 3A input Gate 3 input A; TTL-compatible input that is overvoltage tolerant up to 5.5 V at any valid VCC, and high impedance when VCC = 0 V.
10 3B input Gate 3 input B; TTL-compatible input that is overvoltage tolerant up to 5.5 V at any valid VCC, and unused inputs must be held at VCC or GND.
11 4Y output Gate 4 output Y; low-drive CMOS output that should not exceed 25 mA load current and should not be pulled above VCC.
12 4A input Gate 4 input A; TTL-compatible input that is overvoltage tolerant up to 5.5 V at any valid VCC, and high impedance when VCC = 0 V.
13 4B input Gate 4 input B; TTL-compatible input that is overvoltage tolerant up to 5.5 V at any valid VCC, and unused inputs must be held at VCC or GND.
14 VCC power_in Positive supply, 4.5 V to 5.5 V per recommended operating conditions, with a 0.1 µF bypass capacitor placed close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: SN74AHCT08QDRQ1
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: sn74ahct08qdrq1-etched.step / sn74ahct08qdrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ahct08qdrq1.step / sn74ahct08qdrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 b20353342d7a5006, retrieved 2026-10-09, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF