component
SN74AHCT00N
Public Made by Adomby adom
Texas Instruments Logic Gates, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
SN74AHCT00N
Texas Instruments · Logic Gates · PDIP-14
SN74AHCT00N from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Channel 1 input A of the 2-input NAND gate; unused inputs must be tied to VCC or GND, and the input must not be left floating. |
| 2 | 1B | input | Channel 1 input B of the 2-input NAND gate; unused inputs must be tied to VCC or GND, and the input must not be left floating. |
| 3 | 1Y | output | Channel 1 NAND gate output Y; outputs must not be tied directly to VCC or GND, and push-pull outputs must never be connected together. |
| 4 | 2A | input | Channel 2 input A of the 2-input NAND gate; unused inputs must be tied to VCC or GND, and the input must not be left floating. |
| 5 | 2B | input | Channel 2 input B of the 2-input NAND gate; unused inputs must be tied to VCC or GND, and the input must not be left floating. |
| 6 | 2Y | output | Channel 2 NAND gate output Y; outputs must not be tied directly to VCC or GND, and push-pull outputs must never be connected together. |
| 7 | GND | power_in | Ground reference for the device; the ground pin must be able to sink the total output current plus ICC and transient currents, and the absolute maximum continuous current through GND is ±50 mA. |
| 8 | 3Y | output | Channel 3 NAND gate output Y; outputs must not be tied directly to VCC or GND, and push-pull outputs must never be connected together. |
| 9 | 3A | input | Channel 3 input A of the 2-input NAND gate; unused inputs must be tied to VCC or GND, and the input must not be left floating. |
| 10 | 3B | input | Channel 3 input B of the 2-input NAND gate; unused inputs must be tied to VCC or GND, and the input must not be left floating. |
| 11 | 4Y | output | Channel 4 NAND gate output Y; outputs must not be tied directly to VCC or GND, and push-pull outputs must never be connected together. |
| 12 | 4A | input | Channel 4 input A of the 2-input NAND gate; unused inputs must be tied to VCC or GND, and the input must not be left floating. |
| 13 | 4B | input | Channel 4 input B of the 2-input NAND gate; unused inputs must be tied to VCC or GND, and the input must not be left floating. |
| 14 | VCC | power_in | Positive supply; the recommended operating supply range is 4.5 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.5 | 5.5 | V | SN74AHCT00 column | 5 | |
| High-level input voltage | VIH | 2 | V | SN74AHCT00 column | 5 | ||
| Low-level input voltage | VIL | 0.8 | V | SN74AHCT00 column | 5 | ||
| Input voltage | VI | 0 | 5.5 | V | SN74AHCT00 column | 5 | |
| Output voltage | VO | 0 | V | Maximum printed as VCC; not numeric | 5 | ||
| High-level output current | IOH | -8 | mA | SN74AHCT00 column; single printed value placed in max column | 5 | ||
| Low-level output current | IOL | 8 | mA | SN74AHCT00 column; single printed value placed in max column | 5 | ||
| Input transition rise or fall rate | Δt/Δv | 20 | ns/V | SN74AHCT00 column; single printed value placed in max column | 5 | ||
| Operating free-air temperature | TA | -40 | 85 | °C | SN74AHCT00 column | 5 | |
| Supply voltage range | VCC | -0.5 | 7 | V | 5 | ||
| Input voltage range | VI | -0.5 | 7 | V | 5 | ||
| Output voltage range | VO | -0.5 | V | Maximum printed as VCC + 0.5 V; not numeric | 5 | ||
| Input clamp current | IIK | -20 | mA | VI < -0.5 V | 5 | ||
| Output clamp current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 5 | |
| Continuous output current | IO | -25 | 25 | mA | VO = 0 to VCC | 5 | |
| Continuous output current through VCC or GND | -50 | 50 | mA | 5 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| High-level output voltage | VOH | 4.4 | 4.5 | V | IOH = -50 µA; VCC 4.5 V; TA = 25°C typ | 6 | |
| High-level output voltage | VOH | 3.8 | 3.94 | V | IOH = -8 mA; VCC 4.5 V; TA = 25°C typ | 6 | |
| Low-level output voltage | VOL | 0.1 | 0.1 | V | IOL = 50 µA; VCC 4.5 V; TA = 25°C typ | 6 | |
| Low-level output voltage | VOL | 0.36 | 0.44 | V | IOL = 8 mA; VCC 4.5 V; TA = 25°C typ | 6 | |
| Input leakage current | II | -1 | 0.1 | 1 | µA | VI = 5.5 V or GND; VCC 0 V to 5.5 V; typ printed ±0.1 | 6 |
| Quiescent supply current | ICC | 2 | 20 | µA | VI = VCC or GND; IO = 0; VCC 5.5 V | 6 | |
| Supply current increase per input | ΔICC | 1.35 | 1.5 | mA | One input at 3.4 V, other inputs at VCC or GND; VCC 5.5 V | 6 | |
| Input capacitance | Ci | 2 | 10 | pF | VI = VCC or GND; VCC 5 V | 6 | |
| Propagation delay low-to-high | tPLH | 1 | 5 | 8 | ns | VCC = 5 V ± 0.5 V; CL = 15 pF; A or B to Y; TA = 25°C typ | 6 |
| Propagation delay high-to-low | tPHL | 1 | 5 | 8 | ns | VCC = 5 V ± 0.5 V; CL = 15 pF; A or B to Y; TA = 25°C typ | 6 |
| Propagation delay low-to-high | tPLH | 1 | 5.5 | 9 | ns | VCC = 5 V ± 0.5 V; CL = 50 pF; A or B to Y; TA = 25°C typ | 6 |
| Propagation delay high-to-low | tPHL | 1 | 5.5 | 9 | ns | VCC = 5 V ± 0.5 V; CL = 50 pF; A or B to Y; TA = 25°C typ | 6 |
| Junction-to-ambient thermal resistance (PDIP N package) | RθJA | 80 | °C/W | N (PDIP) package, 14 pins | 6 |
CAD (KiCad official)
- Symbol:
SN74AHCT00N - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74ahct00n-etched.step/sn74ahct00n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ahct00n.step/sn74ahct00n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (43 pp, sha256
f8260ae34dd0c6d7, retrieved 2026-10-16, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74AHCT00N
**Texas Instruments** · Logic Gates · PDIP-14
SN74AHCT00N from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Channel 1 input A of the 2-input NAND gate; unused inputs must be tied to VCC or GND, and the input must not be left floating. |
| 2 | 1B | input | Channel 1 input B of the 2-input NAND gate; unused inputs must be tied to VCC or GND, and the input must not be left floating. |
| 3 | 1Y | output | Channel 1 NAND gate output Y; outputs must not be tied directly to VCC or GND, and push-pull outputs must never be connected together. |
| 4 | 2A | input | Channel 2 input A of the 2-input NAND gate; unused inputs must be tied to VCC or GND, and the input must not be left floating. |
| 5 | 2B | input | Channel 2 input B of the 2-input NAND gate; unused inputs must be tied to VCC or GND, and the input must not be left floating. |
| 6 | 2Y | output | Channel 2 NAND gate output Y; outputs must not be tied directly to VCC or GND, and push-pull outputs must never be connected together. |
| 7 | GND | power_in | Ground reference for the device; the ground pin must be able to sink the total output current plus ICC and transient currents, and the absolute maximum continuous current through GND is ±50 mA. |
| 8 | 3Y | output | Channel 3 NAND gate output Y; outputs must not be tied directly to VCC or GND, and push-pull outputs must never be connected together. |
| 9 | 3A | input | Channel 3 input A of the 2-input NAND gate; unused inputs must be tied to VCC or GND, and the input must not be left floating. |
| 10 | 3B | input | Channel 3 input B of the 2-input NAND gate; unused inputs must be tied to VCC or GND, and the input must not be left floating. |
| 11 | 4Y | output | Channel 4 NAND gate output Y; outputs must not be tied directly to VCC or GND, and push-pull outputs must never be connected together. |
| 12 | 4A | input | Channel 4 input A of the 2-input NAND gate; unused inputs must be tied to VCC or GND, and the input must not be left floating. |
| 13 | 4B | input | Channel 4 input B of the 2-input NAND gate; unused inputs must be tied to VCC or GND, and the input must not be left floating. |
| 14 | VCC | power_in | Positive supply; the recommended operating supply range is 4.5 V to 5.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.5 | | 5.5 | V | SN74AHCT00 column | 5 |
| High-level input voltage | VIH | 2 | | | V | SN74AHCT00 column | 5 |
| Low-level input voltage | VIL | | | 0.8 | V | SN74AHCT00 column | 5 |
| Input voltage | VI | 0 | | 5.5 | V | SN74AHCT00 column | 5 |
| Output voltage | VO | 0 | | | V | Maximum printed as VCC; not numeric | 5 |
| High-level output current | IOH | | | -8 | mA | SN74AHCT00 column; single printed value placed in max column | 5 |
| Low-level output current | IOL | | | 8 | mA | SN74AHCT00 column; single printed value placed in max column | 5 |
| Input transition rise or fall rate | Δt/Δv | | | 20 | ns/V | SN74AHCT00 column; single printed value placed in max column | 5 |
| Operating free-air temperature | TA | -40 | | 85 | °C | SN74AHCT00 column | 5 |
| Supply voltage range | VCC | -0.5 | | 7 | V | | 5 |
| Input voltage range | VI | -0.5 | | 7 | V | | 5 |
| Output voltage range | VO | -0.5 | | | V | Maximum printed as VCC + 0.5 V; not numeric | 5 |
| Input clamp current | IIK | -20 | | | mA | VI < -0.5 V | 5 |
| Output clamp current | IOK | -20 | | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 5 |
| Continuous output current | IO | -25 | | 25 | mA | VO = 0 to VCC | 5 |
| Continuous output current through VCC or GND | | -50 | | 50 | mA | | 5 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 5 |
| High-level output voltage | VOH | 4.4 | 4.5 | | V | IOH = -50 µA; VCC 4.5 V; TA = 25°C typ | 6 |
| High-level output voltage | VOH | 3.8 | 3.94 | | V | IOH = -8 mA; VCC 4.5 V; TA = 25°C typ | 6 |
| Low-level output voltage | VOL | | 0.1 | 0.1 | V | IOL = 50 µA; VCC 4.5 V; TA = 25°C typ | 6 |
| Low-level output voltage | VOL | | 0.36 | 0.44 | V | IOL = 8 mA; VCC 4.5 V; TA = 25°C typ | 6 |
| Input leakage current | II | -1 | 0.1 | 1 | µA | VI = 5.5 V or GND; VCC 0 V to 5.5 V; typ printed ±0.1 | 6 |
| Quiescent supply current | ICC | | 2 | 20 | µA | VI = VCC or GND; IO = 0; VCC 5.5 V | 6 |
| Supply current increase per input | ΔICC | | 1.35 | 1.5 | mA | One input at 3.4 V, other inputs at VCC or GND; VCC 5.5 V | 6 |
| Input capacitance | Ci | | 2 | 10 | pF | VI = VCC or GND; VCC 5 V | 6 |
| Propagation delay low-to-high | tPLH | 1 | 5 | 8 | ns | VCC = 5 V ± 0.5 V; CL = 15 pF; A or B to Y; TA = 25°C typ | 6 |
| Propagation delay high-to-low | tPHL | 1 | 5 | 8 | ns | VCC = 5 V ± 0.5 V; CL = 15 pF; A or B to Y; TA = 25°C typ | 6 |
| Propagation delay low-to-high | tPLH | 1 | 5.5 | 9 | ns | VCC = 5 V ± 0.5 V; CL = 50 pF; A or B to Y; TA = 25°C typ | 6 |
| Propagation delay high-to-low | tPHL | 1 | 5.5 | 9 | ns | VCC = 5 V ± 0.5 V; CL = 50 pF; A or B to Y; TA = 25°C typ | 6 |
| Junction-to-ambient thermal resistance (PDIP N package) | RθJA | | 80 | | °C/W | N (PDIP) package, 14 pins | 6 |
## CAD (KiCad official)
- Symbol: `SN74AHCT00N`
- Footprint: `Package_DIP:DIP-14_W7.62mm`
- 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files: `sn74ahct00n-etched.step` / `sn74ahct00n-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ahct00n.step` / `sn74ahct00n.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74ahct00) (43 pp, sha256 `f8260ae34dd0c6d7`, retrieved 2026-10-16, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74ahct00n-datasheet.pdf)