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Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	11d ago
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sn74ahc74qpwrg4q1-etched.glb	sn74ahc74qpwrg4q1: factory component page (tier=lcsc) · Ray	11d ago
sn74ahc74qpwrg4q1-etched.step	sn74ahc74qpwrg4q1: factory component page (tier=lcsc) · Ray	11d ago
sn74ahc74qpwrg4q1-hero.glb	sn74ahc74qpwrg4q1: hero GLB from the etched model (keeps the MPN mark) · Ray	11d ago
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sn74ahc74qpwrg4q1.glb	Publish 0.1.0 · Ray	11d ago
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sn74ahc74qpwrg4q1.step	Publish 0.1.0 · Ray	11d ago

SN74AHC74QPWRG4Q1

Texas Instruments · Flip Flops · TSSOP-14

SN74AHC74QPWRG4Q1 from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1CLR	input	Channel 1 asynchronous clear, active low; a low level on CLR resets 1Q low regardless of the other inputs.
2	1D	input	Channel 1 data input, transferred to the outputs on the rising edge of 1CLK when PRE and CLR are inactive (high) and the setup and hold times are met.
3	1CLK	input	Channel 1 clock input, positive-edge triggered; the setup time before and the hold time after CLK rising must be met.
4	1PRE	input	Channel 1 asynchronous preset, active low; a low level on PRE sets 1Q high regardless of the other inputs.
5	1Q	output	Channel 1 true output of the balanced CMOS push-pull stage, which follows D on the clock edge.
6	~{1Q}	output	Channel 1 inverted output, the complement of 1Q.
7	GND	power_in	Ground reference.
8	~{2Q}	output	Channel 2 inverted output, the complement of 2Q.
9	2Q	output	Channel 2 true output of the balanced CMOS push-pull stage, which follows D on the clock edge.
10	2PRE	input	Channel 2 asynchronous preset, active low; a low level on PRE sets 2Q high regardless of the other inputs.
11	2CLK	input	Channel 2 clock input, positive-edge triggered; the setup time before and the hold time after CLK rising must be met.
12	2D	input	Channel 2 data input, transferred to the outputs on the rising edge of 2CLK when PRE and CLR are inactive (high) and the setup and hold times are met.
13	2CLR	input	Channel 2 asynchronous clear, active low; a low level on CLR resets 2Q low regardless of the other inputs.
14	VCC	power_in	Positive supply; the recommended operating range is 2 V to 5.5 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-14
Category	Logic
Pins	14

CAD (KiCad official)

Symbol: SN74AHC74QPWRG4Q1
Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
3D model: TSSOP-14 (KiCad packages3D, STEP)
3D model files: sn74ahc74qpwrg4q1-etched.step / sn74ahc74qpwrg4q1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ahc74qpwrg4q1.step / sn74ahc74qpwrg4q1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (32 pp, sha256 12a257995cef7f12, retrieved 2026-10-11, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF