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SN74AHC595QPWRQ1

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Texas Instruments Shifting Register, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74AHC595QPWRQ1

Texas Instruments · Shifting Register · TSSOP-16

SN74AHC595QPWRQ1 from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 QB tri_state QB parallel 3-state storage-register output, placed in high-impedance when OE is high.
2 QC tri_state QC parallel 3-state storage-register output, placed in high-impedance when OE is high.
3 QD tri_state QD parallel 3-state storage-register output, placed in high-impedance when OE is high.
4 QE tri_state QE parallel 3-state storage-register output, placed in high-impedance when OE is high.
5 QF tri_state QF parallel 3-state storage-register output, placed in high-impedance when OE is high.
6 QG tri_state QG parallel 3-state storage-register output, placed in high-impedance when OE is high.
7 QH tri_state QH parallel 3-state storage-register output, placed in high-impedance when OE is high.
8 GND power_in Ground pin.
9 QH' output Serial output of the shift register for cascading, not placed in high-impedance by OE.
10 SRCLR input Direct overriding clear input of the shift register, clearing it when low.
11 SRCLK input Shift-register clock input, positive-edge triggered.
12 RCLK input Storage-register clock input, positive-edge triggered, which stores shift-register data into the storage register.
13 OE input Active-low output enable; when high, outputs QA-QH are in the high-impedance state.
14 SER input Serial data input to the shift register.
15 QA tri_state QA parallel 3-state storage-register output, placed in high-impedance when OE is high.
16 VCC power_in Power supply pin, 2 V to 5.5 V recommended operating range with a 0.1-µF bypass capacitor recommended close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC -0.5 7 V 4
Input voltage range VI -0.5 7 V 4
Output voltage range VO -0.5 V max printed as VCC + 0.5 V 4
Input clamp current IIK -20 mA VI < 0 4
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 4
Continuous output current IO -25 25 mA VO = 0 to VCC 4
Continuous current through VCC or GND -75 75 mA 4
Storage temperature range Tstg -65 150 °C 4
Supply voltage VCC 2 5.5 V 4
High-level input voltage VIH 1.5 V VCC = 2 V 4
High-level input voltage VIH 2.1 V VCC = 3 V 4
High-level input voltage VIH 3.85 V VCC = 5.5 V 4
Low-level input voltage VIL 0.5 V VCC = 2 V 4
Low-level input voltage VIL 0.9 V VCC = 3 V 4
Low-level input voltage VIL 1.65 V VCC = 5.5 V 4
Input voltage VI 0 5.5 V 4
Output voltage VO 0 V max printed as VCC 4
High-level output current IOH -50 µA VCC = 2 V 4
High-level output current IOH -4 mA VCC = 3.3 V ± 0.3 V 4
High-level output current IOH -8 mA VCC = 5 V ± 0.5 V 4
Low-level output current IOL 50 µA VCC = 2 V 4
Low-level output current IOL 4 mA VCC = 3.3 V ± 0.3 V 4
Low-level output current IOL 8 mA VCC = 5 V ± 0.5 V 4
Input transition rise or fall rate Δt/Δv 100 ns/V VCC = 3.3 V ± 0.3 V 4
Input transition rise or fall rate Δt/Δv 20 ns/V VCC = 5 V ± 0.5 V 4
Operating free-air temperature TA -40 125 °C Q-suffix devices 4
Junction-to-ambient thermal resistance RθJA 135.9 °C/W PW (TSSOP) 16 pins 5
High-level output voltage VOH 1.9 2 V IOH = -50 μA, VCC = 2 V 6
High-level output voltage VOH 2.48 V IOH = -4 mA, VCC = 3 V 6
High-level output voltage VOH 3.8 V IOH = -8 mA, VCC = 4.5 V 6
Low-level output voltage VOL 0.1 V IOL = 50 μA, VCC = 2 V 6
Low-level output voltage VOL 0.44 V IOL = 4 mA, VCC = 3 V 6
Input current II -1 1 μA VI = 5.5 V or GND, VCC = 0 V to 5.5 V 6
Off-state output current IOZ -10 10 μA QA-QH, VI = VCC or GND, VO = VCC or GND, OE = VIH or VIL, VCC = 5.5 V 6
Supply current ICC 40 μA VI = VCC or GND, IO = 0, VCC = 5.5 V 6
Input capacitance Ci 3 10 pF VI = VCC or GND, VCC = 5 V 6
Output capacitance Co 5.5 pF VO = VCC or GND, VCC = 5 V 6
Pulse duration SRCLK high or low tw 6.5 ns VCC = 3.3 V ± 0.3 V 6
Pulse duration RCLK high or low tw 6.5 ns VCC = 3.3 V ± 0.3 V 6
Setup time SER before SRCLK↑ tsu 4.5 ns VCC = 3.3 V ± 0.3 V 6
Setup time SRCLK↑ before RCLK↑ tsu 9.5 ns VCC = 3.3 V ± 0.3 V 6
Setup time SRCLR low before RCLK↑ tsu 10 ns VCC = 3.3 V ± 0.3 V 6
Hold time SER after SRCLK↑ th 2.5 ns VCC = 3.3 V ± 0.3 V 6
Pulse duration SRCLK high or low tw 6 ns VCC = 5 V ± 0.5 V 6
Pulse duration RCLK high or low tw 6 ns VCC = 5 V ± 0.5 V 6
Setup time SER before SRCLK↑ tsu 4 ns VCC = 5 V ± 0.5 V 7
Setup time SRCLK↑ before RCLK↑ tsu 6 ns VCC = 5 V ± 0.5 V 7
Setup time SRCLR low before RCLK↑ tsu 6 ns VCC = 5 V ± 0.5 V 7
Hold time SER after SRCLK↑ th 3 ns VCC = 5 V ± 0.5 V 7
Maximum clock frequency fmax 40 105 MHz CL = 50 pF, VCC = 3.3 V ± 0.3 V 8
Propagation delay RCLK to QA-QH tPLH/tPHL 1 7.9 20 ns CL = 50 pF, VCC = 3.3 V ± 0.3 V 8
Propagation delay SRCLK to QH' tPLH/tPHL 1 9.2 21.5 ns CL = 50 pF, VCC = 3.3 V ± 0.3 V 8
Output enable time OE to QA-QH tPZH 1 7.8 20 ns CL = 50 pF, VCC = 3.3 V ± 0.3 V 8
Output enable time OE to QA-QH tPZL 1 9.6 20 ns CL = 50 pF, VCC = 3.3 V ± 0.3 V 8
Maximum clock frequency fmax 75 140 MHz CL = 50 pF, VCC = 5 V ± 0.5 V 8
Propagation delay RCLK to QA-QH tPLH/tPHL 1 5.6 13.5 ns CL = 50 pF, VCC = 5 V ± 0.5 V 8
Propagation delay SRCLK to QH' tPLH/tPHL 1 6.4 14.4 ns CL = 50 pF, VCC = 5 V ± 0.5 V 8
Output enable time OE to QA-QH tPZH 1 5.7 15 ns CL = 50 pF, VCC = 5 V ± 0.5 V 8
Output enable time OE to QA-QH tPZL 1 6.8 15 ns CL = 50 pF, VCC = 5 V ± 0.5 V 8

CAD (KiCad official)

  • Symbol: SN74AHC595QPWRQ1
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74ahc595qpwrq1-etched.step / sn74ahc595qpwrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ahc595qpwrq1.step / sn74ahc595qpwrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 47940eefdc61a19c, retrieved 2026-10-26, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF