component
SN74AHC244MPWREP
Public Made by Adomby adom
Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownSN74AHC244MPWREP
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-20
SN74AHC244MPWREP from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Active-low output enable for the first 4-bit buffer section: when low, 1Y1 to 1Y4 follow 1A1 to 1A4, and when high they go to high impedance; tie OE to VCC through a pull-up resistor to hold the outputs high-Z during power up or down. |
| 2 | 1A1 | input | Data input to buffer channel 1A1; inputs must stay within 0 V to 5.5 V, and unused inputs must be held at VCC or GND. |
| 3 | 2Y4 | tri_state | 3-state output of buffer channel 2A4, enabled by 2OE; output voltage range is 0 V to VCC and continuous output current is limited to ±25 mA. |
| 4 | 1A2 | input | Data input to buffer channel 1A2; inputs must stay within 0 V to 5.5 V, and unused inputs must be held at VCC or GND. |
| 5 | 2Y3 | tri_state | 3-state output of buffer channel 2A3, enabled by 2OE; output voltage range is 0 V to VCC and continuous output current is limited to ±25 mA. |
| 6 | 1A3 | input | Data input to buffer channel 1A3; inputs must stay within 0 V to 5.5 V, and unused inputs must be held at VCC or GND. |
| 7 | 2Y2 | tri_state | 3-state output of buffer channel 2A2, enabled by 2OE; output voltage range is 0 V to VCC and continuous output current is limited to ±25 mA. |
| 8 | 1A4 | input | Data input to buffer channel 1A4; inputs must stay within 0 V to 5.5 V, and unused inputs must be held at VCC or GND. |
| 9 | 2Y1 | tri_state | 3-state output of buffer channel 2A1, enabled by 2OE; output voltage range is 0 V to VCC and continuous output current is limited to ±25 mA. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | 2A1 | input | Data input to buffer channel 2A1; inputs must stay within 0 V to 5.5 V, and unused inputs must be held at VCC or GND. |
| 12 | 1Y4 | tri_state | 3-state output of buffer channel 1A4, enabled by 1OE; output voltage range is 0 V to VCC and continuous output current is limited to ±25 mA. |
| 13 | 2A2 | input | Data input to buffer channel 2A2; inputs must stay within 0 V to 5.5 V, and unused inputs must be held at VCC or GND. |
| 14 | 1Y3 | tri_state | 3-state output of buffer channel 1A3, enabled by 1OE; output voltage range is 0 V to VCC and continuous output current is limited to ±25 mA. |
| 15 | 2A3 | input | Data input to buffer channel 2A3; inputs must stay within 0 V to 5.5 V, and unused inputs must be held at VCC or GND. |
| 16 | 1Y2 | tri_state | 3-state output of buffer channel 1A2, enabled by 1OE; output voltage range is 0 V to VCC and continuous output current is limited to ±25 mA. |
| 17 | 2A4 | input | Data input to buffer channel 2A4; inputs must stay within 0 V to 5.5 V, and unused inputs must be held at VCC or GND. |
| 18 | 1Y1 | tri_state | 3-state output of buffer channel 1A1, enabled by 1OE; output voltage range is 0 V to VCC and continuous output current is limited to ±25 mA. |
| 19 | 2OE | input | Active-low output enable for the second 4-bit buffer section: when low, 2Y1 to 2Y4 follow 2A1 to 2A4, and when high they go to high impedance; tie OE to VCC through a pull-up resistor to hold the outputs high-Z during power up or down. |
| 20 | VCC | power_in | Supply voltage, operating range 2 V to 5.5 V (absolute maximum −0.5 V to 7 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
SN74AHC244MPWREP - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74ahc244mpwrep-etched.step/sn74ahc244mpwrep-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ahc244mpwrep.step/sn74ahc244mpwrep.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (11 pp, sha256
b8095d08df0e0e80, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).