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SN74AHC1G02DCKT
Public Made by Adomby adom
Texas Instruments Logic Gates, SC-70-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74AHC1G02DCKT
Texas Instruments · Logic Gates · SC-70-5
SN74AHC1G02DCKT from Texas Instruments, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Input A of the single 2-input positive-NOR gate, with Schmitt trigger action and inputs tolerant to 5.5 V. |
| 2 | B | input | Input B of the single 2-input positive-NOR gate, with Schmitt trigger action and inputs tolerant to 5.5 V. |
| 3 | GND | power_in | Ground pin for the device. |
| 4 | Y | output | Output Y of the NOR gate (Y = A + B in positive logic), rated for ±8 mA output drive at 5 V. |
| 5 | VCC | power_in | Supply pin; the device operates from 2 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SC-70-5 |
| Category | Logic |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VCC | -0.5 | 7 | V | 4 | ||
| Input voltage range | VI | -0.5 | 7 | V | 4 | ||
| Output voltage range | VO | -0.5 | V | max = VCC + 0.5 V | 4 | ||
| Input clamp current | IIK | -20 | mA | VI < 0 | 4 | ||
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VCC | 4 | |
| Continuous output current | IO | -25 | 25 | mA | VO = 0 to VCC | 4 | |
| Continuous current through each VCC or GND | -50 | 50 | mA | 4 | |||
| Storage temperature range | Tstg | -65 | 150 | °C | 4 | ||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Supply voltage | VCC | 2 | 5.5 | V | 4 | ||
| High-level input voltage | VIH | 1.5 | V | VCC = 2 V | 4 | ||
| High-level input voltage | VIH | 2.1 | V | VCC = 3 V | 4 | ||
| High-level input voltage | VIH | 3.85 | V | VCC = 5.5 V | 4 | ||
| Low-level input voltage | VIL | 0.5 | V | VCC = 2 V | 4 | ||
| Low-level input voltage | VIL | 0.9 | V | VCC = 3 V | 4 | ||
| Low-level input voltage | VIL | 1.65 | V | VCC = 5.5 V | 4 | ||
| Input voltage | VIH | 0 | 5.5 | V | 4 | ||
| Output voltage | VO | 0 | V | max = VCC | 4 | ||
| High-level output current | IOH | -50 | µA | VCC = 2 V | 4 | ||
| High-level output current | IOH | -4 | mA | VCC = 3.3 V ± 0.3 V | 4 | ||
| High-level output current | IOH | -8 | mA | VCC = 5 V ± 0.5 V | 4 | ||
| Low-level output current | IOL | 50 | µA | VCC = 2 V | 4 | ||
| Low-level output current | IOL | 4 | mA | VCC = 3.3 V ± 0.3 V | 4 | ||
| Low-level output current | IOL | 8 | mA | VCC = 5 V ± 0.5 V | 4 | ||
| Input transition rise or fall rate | Δt/Δv | 100 | ns/V | VCC = 3.3 V ± 0.3 V | 4 | ||
| Input transition rise or fall rate | Δt/Δv | 20 | ns/V | VCC = 5 V ± 0.5 V | 4 | ||
| Operating free-air temperature | TA | -40 | 125 | °C | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 289.2 | °C/W | DCK package | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 205.8 | °C/W | DCK package | 5 | ||
| Junction-to-board thermal resistance | RθJB | 176.2 | °C/W | DCK package | 5 | ||
| Junction-to-top characterization parameter | ψJT | 117.6 | °C/W | DCK package | 5 | ||
| Junction-to-board characterization parameter | ψJB | 175.1 | °C/W | DCK package | 5 | ||
| High level output voltage | VOH | 1.9 | V | IOH = -50 µA, VCC = 2 V, TA = -40°C to 125°C | 5 | ||
| High level output voltage | VOH | 2.9 | V | IOH = -50 µA, VCC = 3 V, TA = -40°C to 125°C | 5 | ||
| High level output voltage | VOH | 4.4 | V | IOH = -50 µA, VCC = 4.5 V, TA = -40°C to 125°C | 5 | ||
| High level output voltage | VOH | 2.48 | V | IOH = -4 mA, VCC = 3 V, TA = -40°C to 125°C | 5 | ||
| High level output voltage | VOH | 3.8 | V | IOH = -8 mA, VCC = 4.5 V, TA = -40°C to 125°C | 5 | ||
| Low level output voltage | VOL | 0.1 | V | IOH = 50 µA, VCC = 2 V, TA = -40°C to 125°C | 5 | ||
| Low level output voltage | VOL | 0.44 | V | IOL = 4 mA, VCC = 3 V, TA = -40°C to 125°C | 5 | ||
| Input leakage current | II | -1 | 1 | µA | VI = 5.5 V or GND, 0 V to 5.5 V, TA = -40°C to 125°C | 5 | |
| Supply current | ICC | 10 | µA | VI = VCC or GND, IO = 0, VCC = 5.5 V, TA = -40°C to 125°C | 5 | ||
| Input capacitance | Ci | 10 | pF | VI = VCC or GND, VCC = 5 V, TA = -40°C to 125°C | 5 | ||
| Propagation delay tPLH | tPLH | 1 | 10.5 | ns | VCC = 3.3 V ± 0.3 V, CL = 15 pF, TA = -40°C to 125°C | 6 | |
| Propagation delay tPHL | tPHL | 1 | 10.5 | ns | VCC = 3.3 V ± 0.3 V, CL = 15 pF, TA = -40°C to 125°C | 6 | |
| Propagation delay tPLH | tPLH | 1 | 14 | ns | VCC = 3.3 V ± 0.3 V, CL = 50 pF, TA = -40°C to 125°C | 6 | |
| Propagation delay tPHL | tPHL | 1 | 14 | ns | VCC = 3.3 V ± 0.3 V, CL = 50 pF, TA = -40°C to 125°C | 6 | |
| Propagation delay tPLH | tPLH | 1 | 7 | ns | VCC = 5 V ± 0.5 V, CL = 15 pF, TA = -40°C to 125°C | 6 | |
| Propagation delay tPHL | tPHL | 1 | 7 | ns | VCC = 5 V ± 0.5 V, CL = 15 pF, TA = -40°C to 125°C | 6 | |
| Propagation delay tPLH | tPLH | 1 | 9 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF, TA = -40°C to 125°C | 6 | |
| Propagation delay tPHL | tPHL | 1 | 9 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF, TA = -40°C to 125°C | 6 |
CAD (KiCad official)
- Symbol:
SN74AHC1G02DCKT - Footprint:
Package_TO_SOT_SMD:SOT-353_SC-70-5 - 3D model: SC-70-5 (KiCad packages3D, STEP)
- 3D model files:
sn74ahc1g02dckt-etched.step/sn74ahc1g02dckt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ahc1g02dckt.step/sn74ahc1g02dckt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (26 pp, sha256
99cfc4da49faf337, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74AHC1G02DCKT
**Texas Instruments** · Logic Gates · SC-70-5
SN74AHC1G02DCKT from Texas Instruments, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Input A of the single 2-input positive-NOR gate, with Schmitt trigger action and inputs tolerant to 5.5 V. |
| 2 | B | input | Input B of the single 2-input positive-NOR gate, with Schmitt trigger action and inputs tolerant to 5.5 V. |
| 3 | GND | power_in | Ground pin for the device. |
| 4 | Y | output | Output Y of the NOR gate (Y = A + B in positive logic), rated for ±8 mA output drive at 5 V. |
| 5 | VCC | power_in | Supply pin; the device operates from 2 V to 5.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SC-70-5 |
| Category | Logic |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VCC | -0.5 | | 7 | V | | 4 |
| Input voltage range | VI | -0.5 | | 7 | V | | 4 |
| Output voltage range | VO | -0.5 | | | V | max = VCC + 0.5 V | 4 |
| Input clamp current | IIK | -20 | | | mA | VI < 0 | 4 |
| Output clamp current | IOK | -20 | | 20 | mA | VO < 0 or VO > VCC | 4 |
| Continuous output current | IO | -25 | | 25 | mA | VO = 0 to VCC | 4 |
| Continuous current through each VCC or GND | | -50 | | 50 | mA | | 4 |
| Storage temperature range | Tstg | -65 | | 150 | °C | | 4 |
| Junction temperature | TJ | | | 150 | °C | | 4 |
| Supply voltage | VCC | 2 | | 5.5 | V | | 4 |
| High-level input voltage | VIH | 1.5 | | | V | VCC = 2 V | 4 |
| High-level input voltage | VIH | 2.1 | | | V | VCC = 3 V | 4 |
| High-level input voltage | VIH | 3.85 | | | V | VCC = 5.5 V | 4 |
| Low-level input voltage | VIL | | | 0.5 | V | VCC = 2 V | 4 |
| Low-level input voltage | VIL | | | 0.9 | V | VCC = 3 V | 4 |
| Low-level input voltage | VIL | | | 1.65 | V | VCC = 5.5 V | 4 |
| Input voltage | VIH | 0 | | 5.5 | V | | 4 |
| Output voltage | VO | 0 | | | V | max = VCC | 4 |
| High-level output current | IOH | -50 | | | µA | VCC = 2 V | 4 |
| High-level output current | IOH | -4 | | | mA | VCC = 3.3 V ± 0.3 V | 4 |
| High-level output current | IOH | -8 | | | mA | VCC = 5 V ± 0.5 V | 4 |
| Low-level output current | IOL | | | 50 | µA | VCC = 2 V | 4 |
| Low-level output current | IOL | | | 4 | mA | VCC = 3.3 V ± 0.3 V | 4 |
| Low-level output current | IOL | | | 8 | mA | VCC = 5 V ± 0.5 V | 4 |
| Input transition rise or fall rate | Δt/Δv | | | 100 | ns/V | VCC = 3.3 V ± 0.3 V | 4 |
| Input transition rise or fall rate | Δt/Δv | | | 20 | ns/V | VCC = 5 V ± 0.5 V | 4 |
| Operating free-air temperature | TA | -40 | | 125 | °C | | 5 |
| Junction-to-ambient thermal resistance | RθJA | | 289.2 | | °C/W | DCK package | 5 |
| Junction-to-case (top) thermal resistance | RθJC(top) | | 205.8 | | °C/W | DCK package | 5 |
| Junction-to-board thermal resistance | RθJB | | 176.2 | | °C/W | DCK package | 5 |
| Junction-to-top characterization parameter | ψJT | | 117.6 | | °C/W | DCK package | 5 |
| Junction-to-board characterization parameter | ψJB | | 175.1 | | °C/W | DCK package | 5 |
| High level output voltage | VOH | 1.9 | | | V | IOH = -50 µA, VCC = 2 V, TA = -40°C to 125°C | 5 |
| High level output voltage | VOH | 2.9 | | | V | IOH = -50 µA, VCC = 3 V, TA = -40°C to 125°C | 5 |
| High level output voltage | VOH | 4.4 | | | V | IOH = -50 µA, VCC = 4.5 V, TA = -40°C to 125°C | 5 |
| High level output voltage | VOH | 2.48 | | | V | IOH = -4 mA, VCC = 3 V, TA = -40°C to 125°C | 5 |
| High level output voltage | VOH | 3.8 | | | V | IOH = -8 mA, VCC = 4.5 V, TA = -40°C to 125°C | 5 |
| Low level output voltage | VOL | | | 0.1 | V | IOH = 50 µA, VCC = 2 V, TA = -40°C to 125°C | 5 |
| Low level output voltage | VOL | | | 0.44 | V | IOL = 4 mA, VCC = 3 V, TA = -40°C to 125°C | 5 |
| Input leakage current | II | -1 | | 1 | µA | VI = 5.5 V or GND, 0 V to 5.5 V, TA = -40°C to 125°C | 5 |
| Supply current | ICC | | | 10 | µA | VI = VCC or GND, IO = 0, VCC = 5.5 V, TA = -40°C to 125°C | 5 |
| Input capacitance | Ci | | | 10 | pF | VI = VCC or GND, VCC = 5 V, TA = -40°C to 125°C | 5 |
| Propagation delay tPLH | tPLH | 1 | | 10.5 | ns | VCC = 3.3 V ± 0.3 V, CL = 15 pF, TA = -40°C to 125°C | 6 |
| Propagation delay tPHL | tPHL | 1 | | 10.5 | ns | VCC = 3.3 V ± 0.3 V, CL = 15 pF, TA = -40°C to 125°C | 6 |
| Propagation delay tPLH | tPLH | 1 | | 14 | ns | VCC = 3.3 V ± 0.3 V, CL = 50 pF, TA = -40°C to 125°C | 6 |
| Propagation delay tPHL | tPHL | 1 | | 14 | ns | VCC = 3.3 V ± 0.3 V, CL = 50 pF, TA = -40°C to 125°C | 6 |
| Propagation delay tPLH | tPLH | 1 | | 7 | ns | VCC = 5 V ± 0.5 V, CL = 15 pF, TA = -40°C to 125°C | 6 |
| Propagation delay tPHL | tPHL | 1 | | 7 | ns | VCC = 5 V ± 0.5 V, CL = 15 pF, TA = -40°C to 125°C | 6 |
| Propagation delay tPLH | tPLH | 1 | | 9 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF, TA = -40°C to 125°C | 6 |
| Propagation delay tPHL | tPHL | 1 | | 9 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF, TA = -40°C to 125°C | 6 |
## CAD (KiCad official)
- Symbol: `SN74AHC1G02DCKT`
- Footprint: `Package_TO_SOT_SMD:SOT-353_SC-70-5`
- 3D model: SC-70-5 (KiCad packages3D, STEP)
- 3D model files: `sn74ahc1g02dckt-etched.step` / `sn74ahc1g02dckt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ahc1g02dckt.step` / `sn74ahc1g02dckt.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74ahc1g02.pdf) (26 pp, sha256 `99cfc4da49faf337`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74ahc1g02dckt-datasheet.pdf)