Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

SN74AHC04QDRQ1

Texas Instruments · Inverters · SOIC-14

SN74AHC04QDRQ1 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Input A of inverter channel 1; the input voltage range is 0 V to 5.5 V per the recommended operating conditions.
2 1Y output Output Y of inverter channel 1; the output voltage range is 0 V to VCC and continuous output current is limited to ±25 mA.
3 2A input Input A of inverter channel 2; the input voltage range is 0 V to 5.5 V per the recommended operating conditions.
4 2Y output Output Y of inverter channel 2; the output voltage range is 0 V to VCC and continuous output current is limited to ±25 mA.
5 3A input Input A of inverter channel 3; the input voltage range is 0 V to 5.5 V per the recommended operating conditions.
6 3Y output Output Y of inverter channel 3; the output voltage range is 0 V to VCC and continuous output current is limited to ±25 mA.
7 GND power_in Ground reference for the device.
8 4Y output Output Y of inverter channel 4; the output voltage range is 0 V to VCC and continuous output current is limited to ±25 mA.
9 4A input Input A of inverter channel 4; the input voltage range is 0 V to 5.5 V per the recommended operating conditions.
10 5Y output Output Y of inverter channel 5; the output voltage range is 0 V to VCC and continuous output current is limited to ±25 mA.
11 5A input Input A of inverter channel 5; the input voltage range is 0 V to 5.5 V per the recommended operating conditions.
12 6Y output Output Y of inverter channel 6; the output voltage range is 0 V to VCC and continuous output current is limited to ±25 mA.
13 6A input Input A of inverter channel 6; the input voltage range is 0 V to 5.5 V per the recommended operating conditions.
14 VCC power_in Positive supply; the supply voltage range is 2 V to 5.5 V per the recommended operating conditions.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 2 5.5 V 4
High-level input voltage VIH 1.5 V VCC = 2 V 4
High-level input voltage VIH 2.1 V VCC = 3 V 4
High-level input voltage VIH 3.85 V VCC = 5.5 V 4
Low-level input voltage VIL 0.5 V VCC = 2 V 4
Low-level input voltage VIL 0.9 V VCC = 3 V 4
Low-level input voltage VIL 1.65 V VCC = 5.5 V 4
Input voltage VI 0 5.5 V 4
Output voltage VO 0 V maximum printed as VCC 4
High-level output current IOH -50 μA VCC = 2 V 4
High-level output current IOH -4 mA VCC = 3.3 V ± 0.3 V 4
High-level output current IOH -8 mA VCC = 5 V ± 0.5 V 4
Low-level output current IOL 50 μA VCC = 2 V 4
Low-level output current IOL 4 mA VCC = 3.3 V ± 0.3 V 4
Low-level output current IOL 8 mA VCC = 5 V ± 0.5 V 4
Input transition rise or fall rate Δt/Δv 100 ns/V VCC = 3.3 V ± 0.3 V 4
Input transition rise or fall rate Δt/Δv 20 ns/V VCC = 5 V ± 0.5 V 4
Operating free-air temperature TA -40 125 °C 4
Supply voltage range VCC -0.5 7 V 4
Input voltage range VI -0.5 7 V 4
Output voltage range VO -0.5 V maximum printed as VCC + 0.5 V 4
Input clamp current IIK -20 mA VI < 0 4
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 4
Continuous output current IO -25 25 mA VO = 0 to VCC 4
Continuous current through VCC or GND -50 50 mA 4
Storage temperature range Tstg -65 150 °C 4
Electrostatic discharge (HBM) V(ESD) -1500 1500 V Human body model (HBM) 4
High-level output voltage VOH 1.9 2 V IOH = −50 μA, VCC = 2 V 5
High-level output voltage VOH 2.9 3 V IOH = −50 μA, VCC = 3 V 5
High-level output voltage VOH 4.4 4.5 V IOH = −50 μA, VCC = 4.5 V 5
High-level output voltage VOH 2.48 V IOH = −4 mA, VCC = 3 V 5
High-level output voltage VOH 3.8 V IOH = −8 mA, VCC = 4.5 V 5
Low-level output voltage VOL 0.1 V IOL = 50 μA, VCC = 2 V 5
Low-level output voltage VOL 0.5 V IOL = 4 mA, VCC = 3 V 5
Input leakage current II -1 1 μA VI = 5.5 V or GND, 0 V to 5.5 V 5
Quiescent supply current ICC 20 μA VI = VCC or GND, IO = 0, VCC = 5.5 V 5
Input capacitance Ci 2 10 pF VI = VCC or GND, VCC = 5 V 5
Propagation delay low-to-high, A to Y tPLH 1 5 10.5 ns CL = 15 pF, VCC = 3.3 V ± 0.3 V 5
Propagation delay high-to-low, A to Y tPHL 1 5 10.5 ns CL = 15 pF, VCC = 3.3 V ± 0.3 V 5
Propagation delay low-to-high, A to Y tPLH 1 7.5 13 ns CL = 50 pF, VCC = 3.3 V ± 0.3 V 5
Propagation delay high-to-low, A to Y tPHL 1 7.5 13 ns CL = 50 pF, VCC = 3.3 V ± 0.3 V 5
Propagation delay low-to-high, A to Y tPLH 1 3.8 6.5 ns CL = 15 pF, VCC = 5 V ± 0.5 V 5
Propagation delay high-to-low, A to Y tPHL 1 3.8 6.5 ns CL = 15 pF, VCC = 5 V ± 0.5 V 5
Propagation delay low-to-high, A to Y tPLH 1 5.3 8.5 ns CL = 50 pF, VCC = 5 V ± 0.5 V 5
Propagation delay high-to-low, A to Y tPHL 1 5.3 8.5 ns CL = 50 pF, VCC = 5 V ± 0.5 V 5
Quiet output, maximum dynamic VOL VOL(P) 0.4 V VCC = 5 V, CL = 50 pF, TA = 25°C 6
Quiet output, minimum dynamic VOL VOL(V) -0.4 V VCC = 5 V, CL = 50 pF, TA = 25°C 6
Quiet output, minimum dynamic VOH VOH(V) 4.8 V VCC = 5 V, CL = 50 pF, TA = 25°C 6
High-level dynamic input voltage VIH(D) 3.5 V VCC = 5 V, CL = 50 pF, TA = 25°C 6
Low-level dynamic input voltage VIL(D) 1.5 V VCC = 5 V, CL = 50 pF, TA = 25°C 6
Junction-to-ambient thermal resistance (D, SOIC-14) RθJA 86 °C/W D (SOIC) package, 14 pins 5

CAD (KiCad official)

  • Symbol: SN74AHC04QDRQ1
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: sn74ahc04qdrq1-etched.step / sn74ahc04qdrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ahc04qdrq1.step / sn74ahc04qdrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 0ba2f8f2c85aa8cf, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF