main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers sn74ahc00mdrep: viewers · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Initial commit: component/sn74ahc00mdrep · Ray 1d ago
sn74ahc00mdrep-etched.glb sn74ahc00mdrep: factory component page (tier=lcsc) · Ray 1d ago
sn74ahc00mdrep-etched.step sn74ahc00mdrep: factory component page (tier=lcsc) · Ray 1d ago
sn74ahc00mdrep-hero.glb sn74ahc00mdrep: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
sn74ahc00mdrep-hero.overlay.json Publish 0.1.0 · Ray 1d ago
sn74ahc00mdrep.glb Publish 0.1.0 · Ray 1d ago
sn74ahc00mdrep.kicad_mod Publish 0.1.0 · Ray 1d ago
sn74ahc00mdrep.kicad_sym Publish 0.1.0 · Ray 1d ago
sn74ahc00mdrep.lbr Publish 0.1.0 · Ray 1d ago
sn74ahc00mdrep.step Publish 0.1.0 · Ray 1d ago

SN74AHC00MDREP

Texas Instruments · Logic Gates · SOIC-14

SN74AHC00MDREP from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 NAND input A; input voltage range is 0 V to 5.5 V, and unused inputs must be held at VCC or GND.
2 1B input Gate 1 NAND input B; input voltage range is 0 V to 5.5 V, and unused inputs must be held at VCC or GND.
3 1Y output Gate 1 NAND output; output voltage is limited to 0 V to VCC and continuous output current is ±25 mA maximum.
4 2A input Gate 2 NAND input A; input voltage range is 0 V to 5.5 V, and unused inputs must be held at VCC or GND.
5 2B input Gate 2 NAND input B; input voltage range is 0 V to 5.5 V, and unused inputs must be held at VCC or GND.
6 2Y output Gate 2 NAND output; output voltage is limited to 0 V to VCC and continuous output current is ±25 mA maximum.
7 GND power_in Device ground pin.
8 3Y output Gate 3 NAND output; output voltage is limited to 0 V to VCC and continuous output current is ±25 mA maximum.
9 3A input Gate 3 NAND input A; input voltage range is 0 V to 5.5 V, and unused inputs must be held at VCC or GND.
10 3B input Gate 3 NAND input B; input voltage range is 0 V to 5.5 V, and unused inputs must be held at VCC or GND.
11 4Y output Gate 4 NAND output; output voltage is limited to 0 V to VCC and continuous output current is ±25 mA maximum.
12 4A input Gate 4 NAND input A; input voltage range is 0 V to 5.5 V, and unused inputs must be held at VCC or GND.
13 4B input Gate 4 NAND input B; input voltage range is 0 V to 5.5 V, and unused inputs must be held at VCC or GND.
14 VCC power_in Supply pin; the operating range is 2 V to 5.5 V VCC, with an absolute maximum of 7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: SN74AHC00MDREP
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: sn74ahc00mdrep-etched.step / sn74ahc00mdrep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ahc00mdrep.step / sn74ahc00mdrep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (15 pp, sha256 2d11cae71e0093ff, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF