component

SN74ACT8541PWR

Public Made by Adom

by adom

Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74act8541pwrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers sn74act8541pwr: viewers · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago
sn74act8541pwr-etched.glb Publish 0.1.0 · Ray 5d ago
sn74act8541pwr-etched.step sn74act8541pwr: factory component page (tier=mfr) · Ray 5d ago
sn74act8541pwr-hero.glb sn74act8541pwr: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
sn74act8541pwr-hero.overlay.json Publish 0.1.0 · Ray 5d ago
sn74act8541pwr.glb Publish 0.1.0 · Ray 5d ago
sn74act8541pwr.kicad_mod Publish 0.1.0 · Ray 5d ago
sn74act8541pwr.kicad_sym Publish 0.1.0 · Ray 5d ago
sn74act8541pwr.lbr Publish 0.1.0 · Ray 5d ago
sn74act8541pwr.step Publish 0.1.0 · Ray 5d ago

SN74ACT8541PWR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

SN74ACT8541PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE1 input Output enable input 1, active low; it can force all channels into the high-impedance state together with OE2.
2 A1 input Schmitt-trigger input for channel 1 (TTL-compatible per the features list).
3 A2 input Schmitt-trigger input for channel 2 (TTL-compatible per the features list).
4 A3 input Schmitt-trigger input for channel 3 (TTL-compatible per the features list).
5 A4 input Schmitt-trigger input for channel 4 (TTL-compatible per the features list).
6 A5 input Schmitt-trigger input for channel 5 (TTL-compatible per the features list).
7 A6 input Schmitt-trigger input for channel 6 (TTL-compatible per the features list).
8 A7 input Schmitt-trigger input for channel 7 (TTL-compatible per the features list).
9 A8 input Schmitt-trigger input for channel 8 (TTL-compatible per the features list).
10 GND power_in Ground reference for the device.
11 Y8 output 3-state output for channel 8.
12 Y7 output 3-state output for channel 7.
13 Y6 output 3-state output for channel 6.
14 Y5 output 3-state output for channel 5.
15 Y4 output 3-state output for channel 4.
16 Y3 output 3-state output for channel 3.
17 Y2 output 3-state output for channel 2.
18 Y1 output 3-state output for channel 1.
19 OE2 input Output enable input 2, active low; it can force all channels into the high-impedance state together with OE1.
20 VCC power_in Positive supply; recommended operating range is 4.5 V to 5.5 V, with an absolute maximum of 7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC -0.5 7 V 4
Input voltage range VI -0.5 V Upper limit printed as VCC + 0.5 V 4
Output voltage range VO -0.5 V Upper limit printed as VCC + 0.5 V 4
Input clamp current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
Output clamp current IOK -50 50 mA VO < -0.5 V or VO > VCC + 0.5 V 4
Continuous output current IO -50 50 mA VO = 0 to VCC 4
Continuous current through VCC or GND -200 200 mA 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
Supply voltage VCC 4.5 5.5 V 4
Input voltage VI 0 V Upper limit printed as VCC 4
Output voltage VO 0 V Upper limit printed as VCC 4
High-level output current IOH -24 mA 4.5V ≤ VCC ≤ 5.5V 4
Low-level output current IOL 24 mA 4.5V ≤ VCC ≤ 5.5V 4
Input transition rise or fall rate Δt/Δv 20 ns/V 4.5V ≤ VCC ≤ 5.5V 4
Operating free-air temperature TA -40 125 °C 4
Positive-going input threshold voltage VT+ 1.2 1.5 1.9 V VCC = 4.5V 5
Positive-going input threshold voltage VT+ 1.4 2 V VCC = 5V 5
Positive-going input threshold voltage VT+ 1.4 1.7 2.1 V VCC = 5.5V 5
Negative-going input threshold voltage VT- 0.5 0.9 1.2 V VCC = 4.5V 5
Negative-going input threshold voltage VT- 0.8 1.3 V VCC = 5V 5
Negative-going input threshold voltage VT- 0.6 1 1.4 V VCC = 5.5V 5
Hysteresis (VT+ − VT-) ΔVT 0.4 0.6 1.4 V VCC = 4.5V 5
Hysteresis (VT+ − VT-) ΔVT 0.4 V VCC = 5V 5
Hysteresis (VT+ − VT-) ΔVT 0.4 0.6 1.5 V VCC = 5.5V 5
High-level output voltage VOH 4.4 4.49 V IOH = -50µA, VCC = 4.5V 5
High-level output voltage VOH 5.4 5.49 V IOH = -50µA, VCC = 5.5V 5
High-level output voltage VOH 3.7 V IOH = -24mA, VCC = 4.5V 5
High-level output voltage VOH 4.7 V IOH = -24mA, VCC = 5.5V 5
High-level output voltage VOH 3.85 V IOH = -50mA, VCC = 5.5V 5
Low-level output voltage VOL 0.001 0.1 V IOH = 50µA, VCC = 4.5V 5
Low-level output voltage VOL 0.36 0.5 V IOH = 24mA, VCC = 4.5V 5
Low-level output voltage VOL 1.65 V IOH = 50mA, VCC = 5.5V 5
Input leakage current II -1 0.1 1 µA VI = 5.5V or GND; VCC 0V to 5.5V 5
Off-state (high-impedance) output current IOZ -5 0.25 5 µA VO = VCC or GND; VCC 5.5V 5
Quiescent supply current ICC 2 80 µA VI = VCC or GND, IO = 0; VCC 5.5V 5
Additional quiescent supply current per input ΔICC 0.6 1.5 mA VI = VCC, 2.1V; any input; VCC 4.5V to 5.5V 5
Propagation delay low-to-high (A to Y) tPLH 4.2 5.8 7.1 ns CL = 50 pF; VCC = 5V 6
Propagation delay high-to-low (A to Y) tPHL 5 8.1 9.6 ns CL = 50 pF; VCC = 5V 6
Enable time high (OE to Y) tPZH 6.3 9.5 11.5 ns CL = 50 pF; VCC = 5V 6
Enable time low (OE to Y) tPZL 6.5 10 11.9 ns CL = 50 pF; VCC = 5V 6
Disable time high (OE to Y) tPHZ 5.3 6.8 7.8 ns CL = 50 pF; VCC = 5V 6
Disable time low (OE to Y) tPLZ 3.8 5.2 6.3 ns CL = 50 pF; VCC = 5V 6
Junction-to-ambient thermal resistance (PW, TSSOP) RθJA 126.2 °C/W 4
Junction-to-case (top) thermal resistance (PW, TSSOP) RθJC(top) 68.7 °C/W 4
Junction-to-board thermal resistance (PW, TSSOP) RθJB 77.3 °C/W 4
Junction-to-top characterization parameter (PW, TSSOP) ΨJT 22.3 °C/W 4
Junction-to-board characterization parameter (PW, TSSOP) ΨJB 76.9 °C/W 4

CAD (KiCad official)

  • Symbol: SN74ACT8541PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74act8541pwr-etched.step / sn74act8541pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74act8541pwr.step / sn74act8541pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 b7bba2cb934dbac3, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF