# SN74ACT74PWR

**Texas Instruments** · Flip Flops · TSSOP-14

SN74ACT74PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CLR | input | Input Channel 1 clear input, active low, which resets flip-flop 1. |
| 2 | 1D | input | Input Channel 1 data input for flip-flop 1. |
| 3 | 1CLK | input | Input Channel 1 positive-edge-triggered clock input for flip-flop 1. |
| 4 | 1PRE | input | Input Channel 1 preset input, active low, which sets flip-flop 1. |
| 5 | 1Q | output | Output Channel 1 true output of flip-flop 1. |
| 6 | ~{1Q} | output | Output Channel 1 inverted output of flip-flop 1. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | ~{2Q} | output | Output Channel 2 inverted output of flip-flop 2. |
| 9 | 2Q | output | Output Channel 2 true output of flip-flop 2. |
| 10 | 2PRE | input | Input Channel 2 preset input, active low, which sets flip-flop 2. |
| 11 | 2CLK | input | Input Channel 2 positive-edge-triggered clock input for flip-flop 2. |
| 12 | 2D | input | Input Channel 2 data input for flip-flop 2. |
| 13 | 2CLR | input | Input Channel 2 clear input, active low, which resets flip-flop 2. |
| 14 | VCC | power_in | Positive supply, specified at 4.5 V to 5.5 V for the SN74ACT74. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VCC | -0.5 |  | 7 | V |  | 4 |
| Input clamp current | IIK | -20 |  | 20 | mA | VI < 0 or VI > VCC | 4 |
| Output clamp current | IOK | -20 |  | 20 | mA | VO < 0 or VO > VCC | 4 |
| Continuous output current | IO | -50 |  | 50 | mA | VO = 0 to VCC | 4 |
| Continuous current through VCC or GND |  | -200 |  | 200 | mA |  | 4 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 4 |
| Junction-to-ambient thermal resistance | RθJA |  | 145.7 |  | °C/W | PW (TSSOP) package | 4 |
| Supply voltage | VCC | 4.5 |  | 5.5 | V |  | 4 |
| High-level input voltage | VIH | 2 |  |  | V |  | 4 |
| Low-level input voltage | VIL |  |  | 0.8 | V |  | 4 |
| Input voltage | VI | 0 |  |  | V |  | 4 |
| Output voltage | VO | 0 |  |  | V |  | 4 |
| High-level output current | IOH | -24 |  |  | mA |  | 4 |
| Low-level output current | IOL |  |  | 24 | mA |  | 4 |
| Input transition rise and fall rate | Δt/Δv |  |  | 8 | ns/V |  | 4 |
| Operating free-air temperature | TA | -40 |  | 85 | °C | SN74ACT74 | 4 |
| High-level output voltage | VOH | 4.4 |  |  | V | IOH = -50µA, VCC = 4.5V | 5 |
| High-level output voltage | VOH | 5.4 |  |  | V | IOH = -50µA, VCC = 5.5V | 5 |
| High-level output voltage | VOH | 3.76 |  |  | V | IOH = -24mA, VCC = 4.5V | 5 |
| High-level output voltage | VOH | 4.76 |  |  | V | IOH = -24mA, VCC = 5.5V | 5 |
| Low-level output voltage | VOL |  |  | 0.1 | V | IOL = 50µA, VCC = 4.5V | 5 |
| Low-level output voltage | VOL |  |  | 0.44 | V | IOL = 24mA, VCC = 4.5V | 5 |
| Input current | II | -1 |  | 1 | µA | VI = VCC or GND, VCC = 5.5V | 5 |
| Supply current | ICC |  |  | 20 | µA | VI = VCC or GND, IO = 0, VCC = 5.5V | 5 |
| Increase in supply current per input | ΔICC |  |  | 1.5 | mA | One input at 3.4V, other inputs at GND or VCC, VCC = 5.5V | 5 |
| Clock frequency | fclock |  |  | 125 | MHz |  | 5 |
| Pulse duration PRE or CLR low | tw | 6 |  |  | ns | PRE or CLR low | 5 |
| Pulse duration CLK | tw | 6 |  |  | ns | CLK | 5 |
| Setup time, data before CLK rising | tsu | 3.5 |  |  | ns | Data, before CLK↑ | 5 |
| Hold time, data after CLK rising | th | 0 |  |  | ns | Data, after CLK↑ | 5 |
| Hold time, PRE or CLR inactive | th | 1 |  |  | ns | PRE or CLR inactive | 5 |
| Propagation delay PRE or CLR to Q or Q | tPLH | 2.5 |  | 10.5 | ns | From PRE or CLR to Q or Q, VCC 4.5V to 5.5V | 5 |
| Propagation delay PRE or CLR to Q or Q | tPHL | 3 |  | 11.5 | ns | From PRE or CLR to Q or Q, VCC 4.5V to 5.5V | 5 |
| Propagation delay CLK to Q or Q | tPLH | 4 |  | 13 | ns | From CLK to Q or Q, VCC 4.5V to 5.5V | 6 |
| Propagation delay CLK to Q or Q | tPHL | 3 |  | 11.5 | ns | From CLK to Q or Q, VCC 4.5V to 5.5V | 6 |

## CAD (KiCad official)

- Symbol: `SN74ACT74PWR`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `sn74act74pwr-etched.step` / `sn74act74pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74act74pwr.step` / `sn74act74pwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74act74.pdf) (41 pp, sha256 `1b69b086efedf44d`, retrieved 2026-10-18, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74act74pwr-datasheet.pdf)