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SN74ACT573PWR

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Texas Instruments Latches, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74ACT573PWR

Texas Instruments · Latches · TSSOP-20

SN74ACT573PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Output enable; when high, all eight 3-state outputs are placed in the high-impedance state, and OE does not affect latch operation.
2 1D input Data input to latch 1; inputs accept voltages up to 5.5 V and are TTL-voltage compatible.
3 2D input Data input to latch 2; inputs accept voltages up to 5.5 V and are TTL-voltage compatible.
4 3D input Data input to latch 3; inputs accept voltages up to 5.5 V and are TTL-voltage compatible.
5 4D input Data input to latch 4; inputs accept voltages up to 5.5 V and are TTL-voltage compatible.
6 5D input Data input to latch 5; inputs accept voltages up to 5.5 V and are TTL-voltage compatible.
7 6D input Data input to latch 6; inputs accept voltages up to 5.5 V and are TTL-voltage compatible.
8 7D input Data input to latch 7; inputs accept voltages up to 5.5 V and are TTL-voltage compatible.
9 8D input Data input to latch 8; inputs accept voltages up to 5.5 V and are TTL-voltage compatible.
10 GND power_in Ground reference pin for the device.
11 LE input Latch enable; when high the Q outputs follow the D inputs, and when taken low the Q outputs latch the levels present at the D inputs.
12 8Q tri_state Three-state output of latch 8, which drives highly capacitive or relatively low-impedance loads when enabled.
13 7Q tri_state Three-state output of latch 7, which drives highly capacitive or relatively low-impedance loads when enabled.
14 6Q tri_state Three-state output of latch 6, which drives highly capacitive or relatively low-impedance loads when enabled.
15 5Q tri_state Three-state output of latch 5, which drives highly capacitive or relatively low-impedance loads when enabled.
16 4Q tri_state Three-state output of latch 4, which drives highly capacitive or relatively low-impedance loads when enabled.
17 3Q tri_state Three-state output of latch 3, which drives highly capacitive or relatively low-impedance loads when enabled.
18 2Q tri_state Three-state output of latch 2, which drives highly capacitive or relatively low-impedance loads when enabled.
19 1Q tri_state Three-state output of latch 1, which drives highly capacitive or relatively low-impedance loads when enabled.
20 VCC power_in Supply voltage pin; operates from 4.5 V to 5.5 V and should be bypassed with a good capacitor (0.1 µF recommended) placed close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74ACT573PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74act573pwr-etched.step / sn74act573pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74act573pwr.step / sn74act573pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (36 pp, sha256 41b1f170ca55a187, retrieved 2026-10-11, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF