component
SN74ACT374PWR
Public Made by Adomby adom
Texas Instruments Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74ACT374PWR
Texas Instruments · Flip Flops · TSSOP-20
SN74ACT374PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Output Enable input, active low; when low Q outputs are active, when high outputs are high-impedance |
| 2 | 1Q | tri_state | 3-state Q output of flip-flop 1; high-impedance when OE is high |
| 3 | 1D | input | D input of flip-flop 1, sampled on positive clock edge |
| 4 | 2D | input | D input of flip-flop 2, sampled on positive clock edge |
| 5 | 2Q | tri_state | 3-state Q output of flip-flop 2; high-impedance when OE is high |
| 6 | 3Q | tri_state | 3-state Q output of flip-flop 3; high-impedance when OE is high |
| 7 | 3D | input | D input of flip-flop 3, sampled on positive clock edge |
| 8 | 4D | input | D input of flip-flop 4, sampled on positive clock edge |
| 9 | 4Q | tri_state | 3-state Q output of flip-flop 4; high-impedance when OE is high |
| 10 | GND | power_in | Ground |
| 11 | CLK | input | Clock input, positive edge-triggered; triggers capture of D input levels to Q outputs |
| 12 | 5Q | tri_state | 3-state Q output of flip-flop 5; high-impedance when OE is high |
| 13 | 5D | input | D input of flip-flop 5, sampled on positive clock edge |
| 14 | 6D | input | D input of flip-flop 6, sampled on positive clock edge |
| 15 | 6Q | tri_state | 3-state Q output of flip-flop 6; high-impedance when OE is high |
| 16 | 7Q | tri_state | 3-state Q output of flip-flop 7; high-impedance when OE is high |
| 17 | 7D | input | D input of flip-flop 7, sampled on positive clock edge |
| 18 | 8D | input | D input of flip-flop 8, sampled on positive clock edge |
| 19 | 8Q | tri_state | 3-state Q output of flip-flop 8; high-impedance when OE is high |
| 20 | VCC | power_out | Power supply; 4.5 V to 5.5 V |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
SN74ACT374PWR - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74act374pwr-etched.step/sn74act374pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74act374pwr.step/sn74act374pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (32 pp, sha256
203851606e4a5669, retrieved 2026-09-24, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).