# SN74ACT374N

**Texas Instruments** · Flip Flops · PDIP-20

SN74ACT374N from Texas Instruments, in a PDIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Buffered active-low output enable; when high, the eight Q outputs are forced to the high-impedance state, and OE should be tied to VCC through a pullup resistor to keep outputs high-Z during power up or power down. |
| 2 | 1Q | tri_state | Three-state output of flip-flop 1, which takes the logic level of 1D on the positive CLK transition and drives IOH of -24 mA and IOL of 24 mA. |
| 3 | 1D | input | Data input to flip-flop 1, sampled on the positive transition of CLK, with inputs accepting voltages up to 5.5 V and TTL-voltage compatible. |
| 4 | 2D | input | Data input to flip-flop 2, sampled on the positive transition of CLK, with inputs accepting voltages up to 5.5 V and TTL-voltage compatible. |
| 5 | 2Q | tri_state | Three-state output of flip-flop 2, which takes the logic level of 2D on the positive CLK transition and drives IOH of -24 mA and IOL of 24 mA. |
| 6 | 3Q | tri_state | Three-state output of flip-flop 3, which takes the logic level of 3D on the positive CLK transition and drives IOH of -24 mA and IOL of 24 mA. |
| 7 | 3D | input | Data input to flip-flop 3, sampled on the positive transition of CLK, with inputs accepting voltages up to 5.5 V and TTL-voltage compatible. |
| 8 | 4D | input | Data input to flip-flop 4, sampled on the positive transition of CLK, with inputs accepting voltages up to 5.5 V and TTL-voltage compatible. |
| 9 | 4Q | tri_state | Three-state output of flip-flop 4, which takes the logic level of 4D on the positive CLK transition and drives IOH of -24 mA and IOL of 24 mA. |
| 10 | GND | power_in | Ground reference for the device; all unused inputs must be held at VCC or GND for proper operation. |
| 11 | CLK | input | Clock input; the Q outputs are set to the logic levels present on the D inputs on the positive clock transition, with a minimum pulse width of 5 ns. |
| 12 | 5Q | tri_state | Three-state output of flip-flop 5, which takes the logic level of 5D on the positive CLK transition and drives IOH of -24 mA and IOL of 24 mA. |
| 13 | 5D | input | Data input to flip-flop 5, sampled on the positive transition of CLK, with inputs accepting voltages up to 5.5 V and TTL-voltage compatible. |
| 14 | 6D | input | Data input to flip-flop 6, sampled on the positive transition of CLK, with inputs accepting voltages up to 5.5 V and TTL-voltage compatible. |
| 15 | 6Q | tri_state | Three-state output of flip-flop 6, which takes the logic level of 6D on the positive CLK transition and drives IOH of -24 mA and IOL of 24 mA. |
| 16 | 7Q | tri_state | Three-state output of flip-flop 7, which takes the logic level of 7D on the positive CLK transition and drives IOH of -24 mA and IOL of 24 mA. |
| 17 | 7D | input | Data input to flip-flop 7, sampled on the positive transition of CLK, with inputs accepting voltages up to 5.5 V and TTL-voltage compatible. |
| 18 | 8D | input | Data input to flip-flop 8, sampled on the positive transition of CLK, with inputs accepting voltages up to 5.5 V and TTL-voltage compatible. |
| 19 | 8Q | tri_state | Three-state output of flip-flop 8, which takes the logic level of 8D on the positive CLK transition and drives IOH of -24 mA and IOL of 24 mA. |
| 20 | VCC | power_in | Supply voltage, recommended operation from 4.5 V to 5.5 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-20 |
| Category | Logic ICs |
| Pins | 20 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.5 |  | 5.5 | V |  | 3 |
| High-level input voltage | VIH | 2 |  |  | V |  | 3 |
| Low-level input voltage | VIL |  |  | 0.8 | V |  | 3 |
| Input voltage | VI | 0 |  |  | V |  | 3 |
| Output voltage | VO | 0 |  |  | V |  | 3 |
| High-level output current | IOH |  |  | -24 | mA |  | 3 |
| Low-level output current | IOL |  |  | 24 | mA |  | 3 |
| Input transition rise or fall rate | Δt/Δv |  |  | 8 | ns/V |  | 3 |
| Operating free-air temperature | TA | -40 |  | 85 | °C |  | 3 |
| Supply voltage range | VCC | -0.5 |  | 7 | V |  | 2 |
| Input voltage range | VI | -0.5 |  |  | V |  | 2 |
| Output voltage range | VO | -0.5 |  |  | V |  | 2 |
| Input clamp current | IIK | -20 |  | 20 | mA | VI < 0 or VI > VCC | 2 |
| Output clamp current | IOK | -20 |  | 20 | mA | VO < 0 or VO > VCC | 2 |
| Continuous output current | IO | -50 |  | 50 | mA | VO = 0 to VCC | 2 |
| Continuous current through VCC or GND |  | -200 |  | 200 | mA |  | 2 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 2 |
| Package thermal impedance, N package | θJA |  | 69 |  | °C/W | N package, per JESD 51-7 | 2 |
| High-level output voltage | VOH | 4.4 | 4.49 |  | V | IOH = −50 μA, VCC = 4.5 V | 3 |
| High-level output voltage | VOH | 5.4 | 5.49 |  | V | IOH = −50 μA, VCC = 5.5 V | 3 |
| High-level output voltage | VOH | 3.76 |  |  | V | IOH = −24 mA, VCC = 4.5 V | 3 |
| High-level output voltage | VOH | 4.76 |  |  | V | IOH = −24 mA, VCC = 5.5 V | 3 |
| Low-level output voltage | VOL |  |  | 0.1 | V | IOL = 50 μA, VCC = 4.5 V | 3 |
| Low-level output voltage | VOL |  |  | 0.44 | V | IOL = 24 mA, VCC = 4.5 V | 3 |
| Off-state (high-impedance) output current | IOZ | -2.5 |  | 2.5 | μA | VO = VCC or GND, VCC = 5.5 V | 3 |
| Input current | II | -1 |  | 1 | μA | VI = VCC or GND, VCC = 5.5 V | 3 |
| Supply current | ICC |  | 4 | 40 | μA | VI = VCC or GND, IO = 0, VCC = 5.5 V | 3 |
| Supply current increase per TTL-level input | ΔICC |  | 0.6 | 1.5 | mA | One input at 3.4 V, other inputs at GND or VCC, VCC = 5.5 V | 3 |
| Clock frequency | fclock | 90 |  |  | MHz | VCC = 5 V ± 0.5 V (see Figure 1) | 4 |
| Pulse duration, CLK high or low | tw | 5 |  |  | ns | VCC = 5 V ± 0.5 V (see Figure 1) | 4 |
| Setup time, data before CLK↑ | tsu | 5.5 |  |  | ns | VCC = 5 V ± 0.5 V (see Figure 1) | 4 |
| Hold time, data after CLK↑ | th | 1.5 |  |  | ns | VCC = 5 V ± 0.5 V (see Figure 1) | 4 |
| Maximum clock frequency | fmax | 90 | 160 |  | MHz | VCC = 5 V ± 0.5 V (see Figure 1); typ at TA = 25°C | 4 |
| Propagation delay CLK to Q, low-to-high | tPLH | 2 | 8.5 | 11.5 | ns | VCC = 5 V ± 0.5 V (see Figure 1) | 4 |
| Propagation delay CLK to Q, high-to-low | tPHL | 1.5 | 8 | 11 | ns | VCC = 5 V ± 0.5 V (see Figure 1) | 4 |
| Output enable time OE to Q, high | tPZH | 1.5 | 8 | 10.5 | ns | VCC = 5 V ± 0.5 V (see Figure 1) | 4 |
| Output enable time OE to Q, low | tPZL | 1.5 | 8 | 10.5 | ns | VCC = 5 V ± 0.5 V (see Figure 1) | 4 |
| Output disable time OE to Q, high | tPHZ | 1 | 8.5 | 12.5 | ns | VCC = 5 V ± 0.5 V (see Figure 1) | 4 |
| Output disable time OE to Q, low | tPLZ | 1 | 7 | 10 | ns | VCC = 5 V ± 0.5 V (see Figure 1) | 4 |

## CAD (KiCad official)

- Symbol: `SN74ACT374N`
- Footprint: `Package_DIP:DIP-20_W7.62mm`
- 3D model: PDIP-20 (KiCad packages3D, STEP)
- 3D model files: `sn74act374n-etched.step` / `sn74act374n-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74act374n.step` / `sn74act374n.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74act374n.pdf) (22 pp, sha256 `078de0d471ea43a8`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74act374n-datasheet.pdf)