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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

SN74ACT373PWR

Texas Instruments · Latches · TSSOP-20

SN74ACT373PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OE	input	Output Enable input, active low; OE = L enables normal 3-state output operation, OE = H places all outputs in high-impedance state
2	1Q	tri_state	Q output of latch 1, 3-state output; normal logic levels when OE = L and high-impedance when OE = H
3	1D	input	Data input for latch 1; sampled when LE = H and latched when LE = L
4	2D	input	Data input for latch 2; sampled when LE = H and latched when LE = L
5	2Q	tri_state	Q output of latch 2, 3-state output; normal logic levels when OE = L and high-impedance when OE = H
6	3Q	tri_state	Q output of latch 3, 3-state output; normal logic levels when OE = L and high-impedance when OE = H
7	3D	input	Data input for latch 3; sampled when LE = H and latched when LE = L
8	4D	input	Data input for latch 4; sampled when LE = H and latched when LE = L
9	4Q	tri_state	Q output of latch 4, 3-state output; normal logic levels when OE = L and high-impedance when OE = H
10	GND	power_in	Ground reference voltage
11	LE	input	Latch Enable input, active high; LE = H enables transparent mode (Q follows D), LE = L latches Q at current D state
12	5Q	tri_state	Q output of latch 5, 3-state output; normal logic levels when OE = L and high-impedance when OE = H
13	5D	input	Data input for latch 5; sampled when LE = H and latched when LE = L
14	6D	input	Data input for latch 6; sampled when LE = H and latched when LE = L
15	6Q	tri_state	Q output of latch 6, 3-state output; normal logic levels when OE = L and high-impedance when OE = H
16	7Q	tri_state	Q output of latch 7, 3-state output; normal logic levels when OE = L and high-impedance when OE = H
17	7D	input	Data input for latch 7; sampled when LE = H and latched when LE = L
18	8D	input	Data input for latch 8; sampled when LE = H and latched when LE = L
19	8Q	tri_state	Q output of latch 8, 3-state output; normal logic levels when OE = L and high-impedance when OE = H
20	VCC	power_in	Power supply voltage, recommended operating range 4.5 V to 5.5 V per Section 4.2

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-20
Category	Logic
Pins	20

CAD (KiCad official)

Symbol: SN74ACT373PWR
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model files: sn74act373pwr-etched.step / sn74act373pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74act373pwr.step / sn74act373pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (31 pp, sha256 40715ded7a1ca192, retrieved 2026-09-27, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF