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Initial commit: component/sn74act373mdwrep

Ray ·58eee4228a ·1d ago
2 files changed +328
README.mdadded+56
@@ -0,0 +1,56 @@+# SN74ACT373MDWREP++**Texas Instruments** · Latches · SOIC-20-300mil++SN74ACT373MDWREP from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OE | input | Active-low buffered output enable; when high, all eight Q outputs go to high impedance, and it should be tied to VCC through a pullup resistor to keep the outputs high-Z during power up and power down. |+| 2 | 1Q | tri_state | Three-state output of latch 1, driving highly capacitive or low-impedance loads with IOH of -24 mA and IOL of 24 mA maximum. |+| 3 | 1D | input | Data input to latch 1, TTL-voltage compatible and accepting voltages up to 5.5 V, sampled while LE is high and held on the falling edge of LE. |+| 4 | 2D | input | Data input to latch 2, TTL-voltage compatible and accepting voltages up to 5.5 V, sampled while LE is high and held on the falling edge of LE. |+| 5 | 2Q | tri_state | Three-state output of latch 2, driving highly capacitive or low-impedance loads with IOH of -24 mA and IOL of 24 mA maximum. |+| 6 | 3Q | tri_state | Three-state output of latch 3, driving highly capacitive or low-impedance loads with IOH of -24 mA and IOL of 24 mA maximum. |+| 7 | 3D | input | Data input to latch 3, TTL-voltage compatible and accepting voltages up to 5.5 V, sampled while LE is high and held on the falling edge of LE. |+| 8 | 4D | input | Data input to latch 4, TTL-voltage compatible and accepting voltages up to 5.5 V, sampled while LE is high and held on the falling edge of LE. |+| 9 | 4Q | tri_state | Three-state output of latch 4, driving highly capacitive or low-impedance loads with IOH of -24 mA and IOL of 24 mA maximum. |+| 10 | GND | power_in | Device ground reference for the 4.5 V to 5.5 V supply. |+| 11 | LE | input | Latch enable; when high the Q outputs follow D, and when taken low the Q outputs latch the data present at D (minimum LE high pulse width 7 ns). |+| 12 | 5Q | tri_state | Three-state output of latch 5, driving highly capacitive or low-impedance loads with IOH of -24 mA and IOL of 24 mA maximum. |+| 13 | 5D | input | Data input to latch 5, TTL-voltage compatible and accepting voltages up to 5.5 V, sampled while LE is high and held on the falling edge of LE. |+| 14 | 6D | input | Data input to latch 6, TTL-voltage compatible and accepting voltages up to 5.5 V, sampled while LE is high and held on the falling edge of LE. |+| 15 | 6Q | tri_state | Three-state output of latch 6, driving highly capacitive or low-impedance loads with IOH of -24 mA and IOL of 24 mA maximum. |+| 16 | 7Q | tri_state | Three-state output of latch 7, driving highly capacitive or low-impedance loads with IOH of -24 mA and IOL of 24 mA maximum. |+| 17 | 7D | input | Data input to latch 7, TTL-voltage compatible and accepting voltages up to 5.5 V, sampled while LE is high and held on the falling edge of LE. |+| 18 | 8D | input | Data input to latch 8, TTL-voltage compatible and accepting voltages up to 5.5 V, sampled while LE is high and held on the falling edge of LE. |+| 19 | 8Q | tri_state | Three-state output of latch 8, driving highly capacitive or low-impedance loads with IOH of -24 mA and IOL of 24 mA maximum. |+| 20 | VCC | power_in | Supply voltage, 4.5 V to 5.5 V (recommended operating range); unused inputs must be held at VCC or GND. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-20-300mil |+| Category | Logic |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `SN74ACT373MDWREP`+- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`+- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)+- 3D model files: `sn74act373mdwrep-etched.step` / `sn74act373mdwrep-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74act373mdwrep.step` / `sn74act373mdwrep.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74act373-ep) (10 pp, sha256 `ed1a6b8db3137261`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74act373mdwrep-datasheet.pdf)
page.jsonadded+272
@@ -0,0 +1,272 @@+{+  "slug": "sn74act373mdwrep",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "sn74act373mdwrep",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "sn74act373mdwrep.kicad_sym",+    "sn74act373mdwrep.kicad_mod",+    "sn74act373mdwrep.glb",+    "sn74act373mdwrep.step",+    "sn74act373mdwrep.lbr",+    "docs/hero.png",+    "docs/sn74act373mdwrep-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "sn74act373mdwrep-hero.glb",+    "sn74act373mdwrep-hero.overlay.json"+  ],+  "component": {+    "mpn": "SN74ACT373MDWREP",+    "manufacturer": "Texas Instruments",+    "package": "SOIC-20-300mil",+    "pin_count": 20,+    "category": "Logic",+    "subcategory": "Latches",+    "datasheet": "https://www.ti.com/cn/lit/gpn/sn74act373-ep",+    "parts": {+      "symbol": "sn74act373mdwrep.kicad_sym",+      "footprint": "sn74act373mdwrep.kicad_mod",+      "model_3d": "sn74act373mdwrep-hero.glb",+      "model_3d_plain": "sn74act373mdwrep.glb",+      "model_3d_step": "sn74act373mdwrep-etched.step",+      "model_3d_step_plain": "sn74act373mdwrep.step",+      "lbr": "sn74act373mdwrep.lbr"+    },+    "distributor_links": {+      "lcsc": "C2675299",+      "digikey": "296-22258-2-ND",+      "mouser": "595-SN74ACT373MDWREP"+    },+    "distributor_check": {+      "checked_at": "2026-10-08T16:08:37Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "296-22258-2-ND",+        "status": "found",+        "lifecycle": "Active"+      },+      "mouser": {+        "pn": "595-SN74ACT373MDWREP",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "OE",+        "type": "input",+        "description": "Active-low buffered output enable; when high, all eight Q outputs go to high impedance, and it should be tied to VCC through a pullup resistor to keep the outputs high-Z during power up and power down."+      },+      {+        "number": "2",+        "name": "1Q",+        "type": "tri_state",+        "description": "Three-state output of latch 1, driving highly capacitive or low-impedance loads with IOH of -24 mA and IOL of 24 mA maximum."+      },+      {+        "number": "3",+        "name": "1D",+        "type": "input",+        "description": "Data input to latch 1, TTL-voltage compatible and accepting voltages up to 5.5 V, sampled while LE is high and held on the falling edge of LE."+      },+      {+        "number": "4",+        "name": "2D",+        "type": "input",+        "description": "Data input to latch 2, TTL-voltage compatible and accepting voltages up to 5.5 V, sampled while LE is high and held on the falling edge of LE."+      },+      {+        "number": "5",+        "name": "2Q",+        "type": "tri_state",+        "description": "Three-state output of latch 2, driving highly capacitive or low-impedance loads with IOH of -24 mA and IOL of 24 mA maximum."+      },+      {+        "number": "6",+        "name": "3Q",+        "type": "tri_state",+        "description": "Three-state output of latch 3, driving highly capacitive or low-impedance loads with IOH of -24 mA and IOL of 24 mA maximum."+      },+      {+        "number": "7",+        "name": "3D",+        "type": "input",+        "description": "Data input to latch 3, TTL-voltage compatible and accepting voltages up to 5.5 V, sampled while LE is high and held on the falling edge of LE."+      },+      {+        "number": "8",+        "name": "4D",+        "type": "input",+        "description": "Data input to latch 4, TTL-voltage compatible and accepting voltages up to 5.5 V, sampled while LE is high and held on the falling edge of LE."+      },+      {+        "number": "9",+        "name": "4Q",+        "type": "tri_state",+        "description": "Three-state output of latch 4, driving highly capacitive or low-impedance loads with IOH of -24 mA and IOL of 24 mA maximum."+      },+      {+        "number": "10",+        "name": "GND",+        "type": "power_in",+        "description": "Device ground reference for the 4.5 V to 5.5 V supply."+      },+      {+        "number": "11",+        "name": "LE",+        "type": "input",+        "description": "Latch enable; when high the Q outputs follow D, and when taken low the Q outputs latch the data present at D (minimum LE high pulse width 7 ns)."+      },+      {+        "number": "12",+        "name": "5Q",+        "type": "tri_state",+        "description": "Three-state output of latch 5, driving highly capacitive or low-impedance loads with IOH of -24 mA and IOL of 24 mA maximum."+      },+      {+        "number": "13",+        "name": "5D",+        "type": "input",+        "description": "Data input to latch 5, TTL-voltage compatible and accepting voltages up to 5.5 V, sampled while LE is high and held on the falling edge of LE."+      },+      {+        "number": "14",+        "name": "6D",+        "type": "input",+        "description": "Data input to latch 6, TTL-voltage compatible and accepting voltages up to 5.5 V, sampled while LE is high and held on the falling edge of LE."+      },+      {+        "number": "15",+        "name": "6Q",+        "type": "tri_state",+        "description": "Three-state output of latch 6, driving highly capacitive or low-impedance loads with IOH of -24 mA and IOL of 24 mA maximum."+      },+      {+        "number": "16",+        "name": "7Q",+        "type": "tri_state",+        "description": "Three-state output of latch 7, driving highly capacitive or low-impedance loads with IOH of -24 mA and IOL of 24 mA maximum."+      },+      {+        "number": "17",+        "name": "7D",+        "type": "input",+        "description": "Data input to latch 7, TTL-voltage compatible and accepting voltages up to 5.5 V, sampled while LE is high and held on the falling edge of LE."+      },+      {+        "number": "18",+        "name": "8D",+        "type": "input",+        "description": "Data input to latch 8, TTL-voltage compatible and accepting voltages up to 5.5 V, sampled while LE is high and held on the falling edge of LE."+      },+      {+        "number": "19",+        "name": "8Q",+        "type": "tri_state",+        "description": "Three-state output of latch 8, driving highly capacitive or low-impedance loads with IOH of -24 mA and IOL of 24 mA maximum."+      },+      {+        "number": "20",+        "name": "VCC",+        "type": "power_in",+        "description": "Supply voltage, 4.5 V to 5.5 V (recommended operating range); unused inputs must be held at VCC or GND."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-5-5",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "extractor flagged: Pin-to-number mapping was reconstructed from the extracted text, where pin numbers 1-10 and 20-11 ar; The datasheet specifies a single package (DW, 20-pin SOIC) for this orderable part, so no other pack"+        ],+        "pages_sent": 10,+        "cost_usd": 0.0632,+        "at": "2026-10-08T16:08:16"+      },+      "datasheet": {+        "url": "https://www.ti.com/cn/lit/gpn/sn74act373-ep",+        "pages": 10,+        "sha256": "ed1a6b8db3137261",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 20,+        "described": 20,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    },+    "models_3d": [+      {+        "file": "sn74act373mdwrep.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          10.3,+          12.8,+          2.75+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "59a10b341e6972b31d81802a048060326da627d8b92dcf4263064f4f62ec808e",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "sn74act373mdwrep-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          10.3,+          12.8,+          2.75+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "28b844b826cf5090b2717aa9c34b72e9e34d26fd3c86fb9832195f0300a34caf",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file