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SN74ACT373DBR

Texas Instruments · Latches · SSOP-20-208mil

SN74ACT373DBR from Texas Instruments, in a SSOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Buffered output-enable input; when high, all eight Q outputs go to high impedance, and OE should be tied to VCC through a pullup resistor to keep the outputs high-impedance during power up or power down.
2 1Q tri_state Three-state output of latch 1 that can drive high-capacitance or low-impedance bus loads and is high-impedance while OE is high.
3 1D input Data input of latch 1, which passes to 1Q while LE is high and is held when LE is taken low.
4 2D input Data input of latch 2, which passes to 2Q while LE is high and is held when LE is taken low.
5 2Q tri_state Three-state output of latch 2 that can drive high-capacitance or low-impedance bus loads and is high-impedance while OE is high.
6 3Q tri_state Three-state output of latch 3 that can drive high-capacitance or low-impedance bus loads and is high-impedance while OE is high.
7 3D input Data input of latch 3, which passes to 3Q while LE is high and is held when LE is taken low.
8 4D input Data input of latch 4, which passes to 4Q while LE is high and is held when LE is taken low.
9 4Q tri_state Three-state output of latch 4 that can drive high-capacitance or low-impedance bus loads and is high-impedance while OE is high.
10 GND power_in Ground reference pin for the device.
11 LE input Latch enable input; when high the Q outputs follow the D inputs, and when taken low the Q outputs latch the levels present at D.
12 5Q tri_state Three-state output of latch 5 that can drive high-capacitance or low-impedance bus loads and is high-impedance while OE is high.
13 5D input Data input of latch 5, which passes to 5Q while LE is high and is held when LE is taken low.
14 6D input Data input of latch 6, which passes to 6Q while LE is high and is held when LE is taken low.
15 6Q tri_state Three-state output of latch 6 that can drive high-capacitance or low-impedance bus loads and is high-impedance while OE is high.
16 7Q tri_state Three-state output of latch 7 that can drive high-capacitance or low-impedance bus loads and is high-impedance while OE is high.
17 7D input Data input of latch 7, which passes to 7Q while LE is high and is held when LE is taken low.
18 8D input Data input of latch 8, which passes to 8Q while LE is high and is held when LE is taken low.
19 8Q tri_state Three-state output of latch 8 that can drive high-capacitance or low-impedance bus loads and is high-impedance while OE is high.
20 VCC power_in Supply pin; the recommended supply range is 4.5 V to 5.5 V and each VCC pin should have a bypass capacitor placed close to it (0.1 µF for a single supply).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-20-208mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74ACT373DBR
  • Footprint: Package_SO:SSOP-20_5.3x7.2mm_P0.65mm
  • 3D model: SSOP-20-208mil (KiCad packages3D, STEP)
  • 3D model files: sn74act373dbr-etched.step / sn74act373dbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74act373dbr.step / sn74act373dbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 365aa5ce085cfef4, retrieved 2026-10-09, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF