component
SN74ACT16PWR
Public Made by Adomby adom
Texas Instruments Inverters, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74ACT16PWR
Texas Instruments · Inverters · TSSOP-14
SN74ACT16PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Channel 1 Schmitt-trigger inverter input; TTL-compatible and must never be left floating, so unused inputs must be terminated at VCC or GND. |
| 2 | 1Y | output | Channel 1 open-drain output that can only drive low and needs an external pull-up (about 10kΩ is typical) to reach a high level. |
| 3 | 2A | input | Channel 2 Schmitt-trigger inverter input; TTL-compatible and must never be left floating, so unused inputs must be terminated at VCC or GND. |
| 4 | 2Y | output | Channel 2 open-drain output that can only drive low and needs an external pull-up (about 10kΩ is typical) to reach a high level. |
| 5 | 3A | input | Channel 3 Schmitt-trigger inverter input; TTL-compatible and must never be left floating, so unused inputs must be terminated at VCC or GND. |
| 6 | 3Y | output | Channel 3 open-drain output that can only drive low and needs an external pull-up (about 10kΩ is typical) to reach a high level. |
| 7 | GND | power_in | Ground reference; it must sink the total output current plus the maximum supply current, and the total GND current must not exceed the Absolute Maximum Ratings limit. |
| 8 | 4Y | output | Channel 4 open-drain output that can only drive low and needs an external pull-up (about 10kΩ is typical) to reach a high level. |
| 9 | 4A | input | Channel 4 Schmitt-trigger inverter input; TTL-compatible and must never be left floating, so unused inputs must be terminated at VCC or GND. |
| 10 | 5Y | output | Channel 5 open-drain output that can only drive low and needs an external pull-up (about 10kΩ is typical) to reach a high level. |
| 11 | 5A | input | Channel 5 Schmitt-trigger inverter input; TTL-compatible and must never be left floating, so unused inputs must be terminated at VCC or GND. |
| 12 | 6Y | output | Channel 6 open-drain output that can only drive low and needs an external pull-up (about 10kΩ is typical) to reach a high level. |
| 13 | 6A | input | Channel 6 Schmitt-trigger inverter input; TTL-compatible and must never be left floating, so unused inputs must be terminated at VCC or GND. |
| 14 | VCC | power_in | Positive supply; the recommended operating range is 4.5 V to 5.5 V and each VCC pin should have a bypass capacitor (0.1 µF recommended) placed close to the device. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VCC | -0.5 | 7 | V | 4 | ||
| Output voltage range | VO | -0.5 | 7 | V | 4 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < -0.5V or VI > VCC + 0.5V | 4 | |
| Output clamp current | IOK | -50 | mA | VO < -0.5V | 4 | ||
| Continuous output current | IO | 50 | mA | VO = 0 to 5.5V | 4 | ||
| Continuous output current through VCC or GND | -200 | 200 | mA | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Electrostatic discharge, human-body model | V(ESD) | -2000 | 2000 | V | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 | 4 | |
| Electrostatic discharge, charged-device model | V(ESD) | -1000 | 1000 | V | Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002 | 4 | |
| Supply voltage | VCC | 4.5 | 5.5 | V | 4 | ||
| Input voltage | VI | 0 | V | 4 | |||
| Output voltage | VO | 0 | 5.5 | V | 4 | ||
| Low-level output current | IOL | 24 | mA | 4 | |||
| Operating free-air temperature | TA | -40 | 125 | °C | 4 | ||
| Positive-going input threshold voltage | VT+ | 1.24 | 1.56 | 1.9 | V | VCC = 4.5 V | 5 |
| Positive-going input threshold voltage | VT+ | 1.32 | 1.65 | 2 | V | VCC = 5 V | 5 |
| Positive-going input threshold voltage | VT+ | 1.4 | 1.74 | 2.1 | V | VCC = 5.5 V | 5 |
| Negative-going input threshold voltage | VT- | 0.67 | 0.91 | 1.18 | V | VCC = 4.5 V | 5 |
| Negative-going input threshold voltage | VT- | 0.7 | 0.95 | 1.23 | V | VCC = 5 V | 5 |
| Negative-going input threshold voltage | VT- | 0.73 | 0.99 | 1.28 | V | VCC = 5.5 V | 5 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.51 | 0.65 | 0.8 | V | VCC = 4.5 V | 5 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.55 | 0.7 | 0.86 | V | VCC = 5 V | 5 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.6 | 0.75 | 0.92 | V | VCC = 5.5 V | 5 |
| Low-level output voltage | VOL | 0.001 | 0.1 | V | IOL = 50 µA; VCC = 4.5 V | 5 | |
| Low-level output voltage | VOL | 0.5 | V | IOL = 24 mA; VCC = 4.5 V | 5 | ||
| Low-level output voltage | VOL | 1.65 | V | IOL = 75 mA; VCC = 5.5 V; duration not to exceed 2 ms | 5 | ||
| Input leakage current | II | -1 | 1 | µA | VI = 5.5 V or GND; VCC 0 to 5.5 V | 5 | |
| Quiescent supply current | ICC | 2 | µA | VI = VCC or GND, IO = 0; VCC = 5.5 V | 5 | ||
| Additional supply current per input | ΔICC | 1.5 | mA | VI = VCC - 2.1 V; any input; VCC 4.5 to 5.5 V | 5 | ||
| Propagation delay, output low to high-Z | tPLZ | 5.3 | 7.2 | ns | CL = 50 pF; VCC = 5 V; A to Y | 5 | |
| Propagation delay, output high-Z to low | tPZL | 4 | 5.9 | ns | CL = 50 pF; VCC = 5 V; A to Y | 5 | |
| Junction-to-ambient thermal resistance | RθJA | 132.2 | °C/W | PW (TSSOP) 14-pin package | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 64.8 | °C/W | PW (TSSOP) 14-pin package | 4 | ||
| Junction-to-board thermal resistance | RθJB | 88.4 | °C/W | PW (TSSOP) 14-pin package | 4 | ||
| Junction-to-top characterization parameter | ΨJT | 11.9 | °C/W | PW (TSSOP) 14-pin package | 4 | ||
| Junction-to-board characterization parameter | ΨJB | 87.4 | °C/W | PW (TSSOP) 14-pin package | 4 |
CAD (KiCad official)
- Symbol:
SN74ACT16PWR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74act16pwr-etched.step/sn74act16pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74act16pwr.step/sn74act16pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (28 pp, sha256
b391cabf1236c5ac, retrieved 2026-10-19, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74ACT16PWR
**Texas Instruments** · Inverters · TSSOP-14
SN74ACT16PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Channel 1 Schmitt-trigger inverter input; TTL-compatible and must never be left floating, so unused inputs must be terminated at VCC or GND. |
| 2 | 1Y | output | Channel 1 open-drain output that can only drive low and needs an external pull-up (about 10kΩ is typical) to reach a high level. |
| 3 | 2A | input | Channel 2 Schmitt-trigger inverter input; TTL-compatible and must never be left floating, so unused inputs must be terminated at VCC or GND. |
| 4 | 2Y | output | Channel 2 open-drain output that can only drive low and needs an external pull-up (about 10kΩ is typical) to reach a high level. |
| 5 | 3A | input | Channel 3 Schmitt-trigger inverter input; TTL-compatible and must never be left floating, so unused inputs must be terminated at VCC or GND. |
| 6 | 3Y | output | Channel 3 open-drain output that can only drive low and needs an external pull-up (about 10kΩ is typical) to reach a high level. |
| 7 | GND | power_in | Ground reference; it must sink the total output current plus the maximum supply current, and the total GND current must not exceed the Absolute Maximum Ratings limit. |
| 8 | 4Y | output | Channel 4 open-drain output that can only drive low and needs an external pull-up (about 10kΩ is typical) to reach a high level. |
| 9 | 4A | input | Channel 4 Schmitt-trigger inverter input; TTL-compatible and must never be left floating, so unused inputs must be terminated at VCC or GND. |
| 10 | 5Y | output | Channel 5 open-drain output that can only drive low and needs an external pull-up (about 10kΩ is typical) to reach a high level. |
| 11 | 5A | input | Channel 5 Schmitt-trigger inverter input; TTL-compatible and must never be left floating, so unused inputs must be terminated at VCC or GND. |
| 12 | 6Y | output | Channel 6 open-drain output that can only drive low and needs an external pull-up (about 10kΩ is typical) to reach a high level. |
| 13 | 6A | input | Channel 6 Schmitt-trigger inverter input; TTL-compatible and must never be left floating, so unused inputs must be terminated at VCC or GND. |
| 14 | VCC | power_in | Positive supply; the recommended operating range is 4.5 V to 5.5 V and each VCC pin should have a bypass capacitor (0.1 µF recommended) placed close to the device. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VCC | -0.5 | | 7 | V | | 4 |
| Output voltage range | VO | -0.5 | | 7 | V | | 4 |
| Input clamp current | IIK | -20 | | 20 | mA | VI < -0.5V or VI > VCC + 0.5V | 4 |
| Output clamp current | IOK | -50 | | | mA | VO < -0.5V | 4 |
| Continuous output current | IO | | | 50 | mA | VO = 0 to 5.5V | 4 |
| Continuous output current through VCC or GND | | -200 | | 200 | mA | | 4 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| Junction temperature | TJ | | | 150 | °C | | 4 |
| Electrostatic discharge, human-body model | V(ESD) | -2000 | | 2000 | V | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 | 4 |
| Electrostatic discharge, charged-device model | V(ESD) | -1000 | | 1000 | V | Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002 | 4 |
| Supply voltage | VCC | 4.5 | | 5.5 | V | | 4 |
| Input voltage | VI | 0 | | | V | | 4 |
| Output voltage | VO | 0 | | 5.5 | V | | 4 |
| Low-level output current | IOL | | | 24 | mA | | 4 |
| Operating free-air temperature | TA | -40 | | 125 | °C | | 4 |
| Positive-going input threshold voltage | VT+ | 1.24 | 1.56 | 1.9 | V | VCC = 4.5 V | 5 |
| Positive-going input threshold voltage | VT+ | 1.32 | 1.65 | 2 | V | VCC = 5 V | 5 |
| Positive-going input threshold voltage | VT+ | 1.4 | 1.74 | 2.1 | V | VCC = 5.5 V | 5 |
| Negative-going input threshold voltage | VT- | 0.67 | 0.91 | 1.18 | V | VCC = 4.5 V | 5 |
| Negative-going input threshold voltage | VT- | 0.7 | 0.95 | 1.23 | V | VCC = 5 V | 5 |
| Negative-going input threshold voltage | VT- | 0.73 | 0.99 | 1.28 | V | VCC = 5.5 V | 5 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.51 | 0.65 | 0.8 | V | VCC = 4.5 V | 5 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.55 | 0.7 | 0.86 | V | VCC = 5 V | 5 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.6 | 0.75 | 0.92 | V | VCC = 5.5 V | 5 |
| Low-level output voltage | VOL | | 0.001 | 0.1 | V | IOL = 50 µA; VCC = 4.5 V | 5 |
| Low-level output voltage | VOL | | | 0.5 | V | IOL = 24 mA; VCC = 4.5 V | 5 |
| Low-level output voltage | VOL | | | 1.65 | V | IOL = 75 mA; VCC = 5.5 V; duration not to exceed 2 ms | 5 |
| Input leakage current | II | -1 | | 1 | µA | VI = 5.5 V or GND; VCC 0 to 5.5 V | 5 |
| Quiescent supply current | ICC | | | 2 | µA | VI = VCC or GND, IO = 0; VCC = 5.5 V | 5 |
| Additional supply current per input | ΔICC | | | 1.5 | mA | VI = VCC - 2.1 V; any input; VCC 4.5 to 5.5 V | 5 |
| Propagation delay, output low to high-Z | tPLZ | | 5.3 | 7.2 | ns | CL = 50 pF; VCC = 5 V; A to Y | 5 |
| Propagation delay, output high-Z to low | tPZL | | 4 | 5.9 | ns | CL = 50 pF; VCC = 5 V; A to Y | 5 |
| Junction-to-ambient thermal resistance | RθJA | | 132.2 | | °C/W | PW (TSSOP) 14-pin package | 4 |
| Junction-to-case (top) thermal resistance | RθJC(top) | | 64.8 | | °C/W | PW (TSSOP) 14-pin package | 4 |
| Junction-to-board thermal resistance | RθJB | | 88.4 | | °C/W | PW (TSSOP) 14-pin package | 4 |
| Junction-to-top characterization parameter | ΨJT | | 11.9 | | °C/W | PW (TSSOP) 14-pin package | 4 |
| Junction-to-board characterization parameter | ΨJB | | 87.4 | | °C/W | PW (TSSOP) 14-pin package | 4 |
## CAD (KiCad official)
- Symbol: `SN74ACT16PWR`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `sn74act16pwr-etched.step` / `sn74act16pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74act16pwr.step` / `sn74act16pwr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74act16.pdf) (28 pp, sha256 `b391cabf1236c5ac`, retrieved 2026-10-19, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74act16pwr-datasheet.pdf)