# SN74ACT10QPWRG4Q1

**Texas Instruments** · Logic Gates · TSSOP-14

SN74ACT10QPWRG4Q1 from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Channel 1, input A of the three-input NAND gate. |
| 2 | 1B | input | Channel 1, input B of the three-input NAND gate. |
| 3 | 2A | input | Channel 2, input A of the three-input NAND gate. |
| 4 | 2B | input | Channel 2, input B of the three-input NAND gate. |
| 5 | 2C | input | Channel 2, input C of the three-input NAND gate. |
| 6 | 2Y | output | Channel 2, output Y of the three-input NAND gate. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | 3Y | output | Channel 3, output Y of the three-input NAND gate. |
| 9 | 3A | input | Channel 3, input A of the three-input NAND gate. |
| 10 | 3B | input | Channel 3, input B of the three-input NAND gate. |
| 11 | 3C | input | Channel 3, input C of the three-input NAND gate. |
| 12 | 1Y | output | Channel 1, output Y of the three-input NAND gate. |
| 13 | 1C | input | Channel 1, input C of the three-input NAND gate. |
| 14 | VCC | power_in | Positive supply; the datasheet specifies 4.5 V to 5.5 V operation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 |  | 7 | V |  | 4 |
| Input voltage range | VI | -0.5 |  |  | V | VCC + 0.5 V as printed | 4 |
| Output voltage range | VO | -0.5 |  |  | V | VCC + 0.5 V as printed | 4 |
| Input clamp current | IIK | -20 |  | 20 | mA | VI < 0 或 VI > VCC | 4 |
| Output clamp current | IOK | -20 |  | 20 | mA | VO < 0 或 VO > VCC | 4 |
| Continuous output current | IO | -50 |  | 50 | mA | VO = 0 至 VCC | 4 |
| Continuous current through VCC or GND |  | -200 |  | 200 | mA |  | 4 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 4 |
| Supply voltage | VCC | 4.5 |  | 5.5 | V |  | 4 |
| High-level input voltage | VIH | 2 |  |  | V |  | 4 |
| Low-level input voltage | VIL |  |  | 0.8 | V |  | 4 |
| Input voltage | VI | 0 |  |  | V | VCC as printed | 4 |
| Output voltage | VO | 0 |  |  | V | VCC as printed | 4 |
| High-level output current | IOH |  |  | -24 | mA |  | 4 |
| Low-level output current | IOL |  |  | 24 | mA |  | 4 |
| Input transition rise or fall rate | Δt/Δv |  |  | 8 | ns/V |  | 4 |
| Operating free-air temperature | TA | -40 |  | 125 | °C |  | 4 |
| Junction-to-ambient thermal resistance | RθJA |  | 145.7 |  | °C/W | PW (TSSOP) 14 引脚 | 4 |
| High-level output voltage | VOH | 4.4 |  |  | V | IOH = -50µA, VCC 4.5V, TA -40°C 至 125°C | 5 |
| High-level output voltage | VOH | 5.4 |  |  | V | IOH = -50µA, VCC 5.5V, TA -40°C 至 125°C | 5 |
| High-level output voltage | VOH | 3.7 |  |  | V | IOH = -24mA, VCC 4.5V, TA -40°C 至 125°C | 5 |
| High-level output voltage | VOH | 4.7 |  |  | V | IOH = -24mA, VCC 5.5V, TA -40°C 至 125°C | 5 |
| High-level output voltage | VOH | 3.85 |  |  | V | IOH = -50mA (1), VCC 5.5V | 5 |
| Low-level output voltage | VOL |  |  | 0.1 | V | IOL = 50µA, VCC 4.5V, TA -40°C 至 125°C | 5 |
| Low-level output voltage | VOL |  |  | 0.5 | V | IOL = 24mA, VCC 4.5V, TA -40°C 至 125°C | 5 |
| Low-level output voltage | VOL |  |  | 1.65 | V | IOL = 50mA (1), VCC 5.5V | 5 |
| Input leakage current | II | -1 |  | 1 | µA | VI = VCC 或 GND, VCC 5.5V | 5 |
| Quiescent supply current | ICC |  | 4 | 80 | µA | VI = VCC 或 GND, IO = 0, VCC 5.5V, TA -40°C 至 125°C max | 5 |
| Change in supply current per TTL input | ΔICC |  | 0.6 | 1.6 | mA | One input at 3.4V, other inputs at GND or VCC, VCC 5.5V, TA -40°C 至 125°C max | 5 |
| Input capacitance | Ci |  | 2.6 |  | pF | VI = VCC 或 GND, VCC 5V | 5 |
| Propagation delay time, low-to-high-level output | tPLH | 1 |  | 10 | ns | VCC = 5V ± 0.5V, from input A/B/C to Y, TA -40°C 至 125°C | 5 |
| Propagation delay time, high-to-low-level output | tPHL | 1 |  | 9.5 | ns | VCC = 5V ± 0.5V, from input A/B/C to Y, TA -40°C 至 125°C | 5 |
| Power dissipation capacitance | Cpd |  | 25 |  | pF | CL = 50pF, f = 1MHz, VCC = 5V, TA = 25°C | 5 |

## CAD (KiCad official)

- Symbol: `SN74ACT10QPWRG4Q1`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `sn74act10qpwrg4q1-etched.step` / `sn74act10qpwrg4q1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74act10qpwrg4q1.step` / `sn74act10qpwrg4q1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74act10-q1) (30 pp, sha256 `3f2e17ba6b782c20`, retrieved 2026-10-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74act10qpwrg4q1-datasheet.pdf)