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SN74ACT00TDRQ1
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74ACT00TDRQ1
Texas Instruments · Logic Gates · SOIC-14
SN74ACT00TDRQ1 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1 input A of the two-input NAND gate (Y = A·B); unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V. |
| 2 | 1B | input | Gate 1 input B of the two-input NAND gate (Y = A·B); unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V. |
| 3 | 1Y | output | Gate 1 NAND output; IOH is -24 mA and IOL is 24 mA, and continuous output current is limited to ±50 mA. |
| 4 | 2A | input | Gate 2 input A of the two-input NAND gate (Y = A·B); unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V. |
| 5 | 2B | input | Gate 2 input B of the two-input NAND gate (Y = A·B); unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V. |
| 6 | 2Y | output | Gate 2 NAND output; IOH is -24 mA and IOL is 24 mA, and continuous output current is limited to ±50 mA. |
| 7 | GND | power_in | Ground reference; continuous current through VCC or GND is limited to ±200 mA. |
| 8 | 3Y | output | Gate 3 NAND output; IOH is -24 mA and IOL is 24 mA, and continuous output current is limited to ±50 mA. |
| 9 | 3A | input | Gate 3 input A of the two-input NAND gate (Y = A·B); unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V. |
| 10 | 3B | input | Gate 3 input B of the two-input NAND gate (Y = A·B); unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V. |
| 11 | 4Y | output | Gate 4 NAND output; IOH is -24 mA and IOL is 24 mA, and continuous output current is limited to ±50 mA. |
| 12 | 4A | input | Gate 4 input A of the two-input NAND gate (Y = A·B); unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V. |
| 13 | 4B | input | Gate 4 input B of the two-input NAND gate (Y = A·B); unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V. |
| 14 | VCC | power_in | Supply voltage, recommended 4.5 V to 5.5 V; absolute maximum 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 3 | ||
| Input voltage | VI | -0.5 | V | Max printed as VCC + 0.5 V | 3 | ||
| Output voltage | VO | -0.5 | V | Max printed as VCC + 0.5 V | 3 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0 or VI > VCC | 3 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VCC | 3 | |
| Continuous output current | IO | -50 | 50 | mA | VO = 0 to VCC | 3 | |
| Continuous current through VCC or GND | -200 | 200 | mA | 3 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Supply voltage | VCC | 4.5 | 5.5 | V | 3 | ||
| High-level input voltage | VIH | 2 | V | 3 | |||
| Low-level input voltage | VIL | 0.8 | V | 3 | |||
| Input voltage | VI | 0 | V | Max printed as VCC | 3 | ||
| Output voltage | VO | 0 | V | Max printed as VCC | 3 | ||
| High-level output current | IOH | -24 | mA | 3 | |||
| Low-level output current | IOL | 24 | mA | 3 | |||
| Input transition rise or fall rate | Δt/Δv | 8 | ns/V | 3 | |||
| Operating free-air temperature | TA | -40 | 105 | °C | 3 | ||
| Junction-to-ambient thermal resistance (D, SOIC-14) | RθJA | 86 | °C/W | 3 | |||
| High-level output voltage | VOH | 4.4 | 4.49 | V | IOH = -50 µA; VCC = 4.5 V; TA = 25°C | 4 | |
| High-level output voltage | VOH | 4.4 | V | IOH = -50 µA; VCC = 4.5 V; full operating temperature range | 4 | ||
| High-level output voltage | VOH | 5.4 | 5.49 | V | IOH = -50 µA; VCC = 5.5 V; TA = 25°C | 4 | |
| High-level output voltage | VOH | 5.4 | V | IOH = -50 µA; VCC = 5.5 V; full operating temperature range | 4 | ||
| High-level output voltage | VOH | 3.86 | V | IOH = -24 mA; VCC = 4.5 V; TA = 25°C | 4 | ||
| High-level output voltage | VOH | 3.7 | V | IOH = -24 mA; VCC = 4.5 V; full operating temperature range | 4 | ||
| High-level output voltage | VOH | 4.86 | V | IOH = -24 mA; VCC = 5.5 V; TA = 25°C | 4 | ||
| High-level output voltage | VOH | 4.7 | V | IOH = -24 mA; VCC = 5.5 V; full operating temperature range | 4 | ||
| Low-level output voltage | VOL | 0.001 | 0.1 | V | IOL = 50 µA; VCC = 4.5 V; TA = 25°C | 4 | |
| Low-level output voltage | VOL | 0.1 | V | IOL = 50 µA; VCC = 4.5 V; full operating temperature range | 4 | ||
| Low-level output voltage | VOL | 0.36 | 0.5 | V | IOL = 24 mA; VCC = 4.5 V | 4 | |
| Input leakage current | II | -0.1 | 0.1 | µA | VI = VCC or GND; VCC = 5.5 V; TA = 25°C | 4 | |
| Input leakage current | II | -1 | 1 | µA | VI = VCC or GND; VCC = 5.5 V; full operating temperature range | 4 | |
| Supply current | ICC | 2 | 40 | µA | VI = VCC or GND, IO = 0; VCC = 5.5 V | 4 | |
| Additional supply current per input at TTL level | ΔICC | 0.6 | 1.6 | mA | One input at 3.4 V, other inputs at GND or VCC; VCC = 5.5 V | 4 | |
| Propagation delay time, low-to-high-level output (A or B to Y) | tPLH | 1.5 | 5.5 | 9 | ns | VCC = 5 V ± 0.5 V; TA = 25°C; see Figure 4-1 | 4 |
| Propagation delay time, low-to-high-level output (A or B to Y) | tPLH | 1 | 9.5 | ns | VCC = 5 V ± 0.5 V; full operating temperature range; see Figure 4-1 | 4 | |
| Propagation delay time, high-to-low-level output (A or B to Y) | tPHL | 1.5 | 4 | 7 | ns | VCC = 5 V ± 0.5 V; TA = 25°C; see Figure 4-1 | 4 |
| Propagation delay time, high-to-low-level output (A or B to Y) | tPHL | 1 | 8 | ns | VCC = 5 V ± 0.5 V; full operating temperature range; see Figure 4-1 | 4 | |
| Input capacitance | Ci | 2.6 | pF | VI = VCC or GND; VCC = 5 V | 4 | ||
| Power dissipation capacitance | Cpd | 40 | pF | CL = 50 pF, f = 1 MHz; VCC = 5 V; TA = 25°C | 4 |
CAD (KiCad official)
- Symbol:
SN74ACT00TDRQ1 - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
sn74act00tdrq1-etched.step/sn74act00tdrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74act00tdrq1.step/sn74act00tdrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
d2227c484855ddfb, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74ACT00TDRQ1
**Texas Instruments** · Logic Gates · SOIC-14
SN74ACT00TDRQ1 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1 input A of the two-input NAND gate (Y = A·B); unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V. |
| 2 | 1B | input | Gate 1 input B of the two-input NAND gate (Y = A·B); unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V. |
| 3 | 1Y | output | Gate 1 NAND output; IOH is -24 mA and IOL is 24 mA, and continuous output current is limited to ±50 mA. |
| 4 | 2A | input | Gate 2 input A of the two-input NAND gate (Y = A·B); unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V. |
| 5 | 2B | input | Gate 2 input B of the two-input NAND gate (Y = A·B); unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V. |
| 6 | 2Y | output | Gate 2 NAND output; IOH is -24 mA and IOL is 24 mA, and continuous output current is limited to ±50 mA. |
| 7 | GND | power_in | Ground reference; continuous current through VCC or GND is limited to ±200 mA. |
| 8 | 3Y | output | Gate 3 NAND output; IOH is -24 mA and IOL is 24 mA, and continuous output current is limited to ±50 mA. |
| 9 | 3A | input | Gate 3 input A of the two-input NAND gate (Y = A·B); unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V. |
| 10 | 3B | input | Gate 3 input B of the two-input NAND gate (Y = A·B); unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V. |
| 11 | 4Y | output | Gate 4 NAND output; IOH is -24 mA and IOL is 24 mA, and continuous output current is limited to ±50 mA. |
| 12 | 4A | input | Gate 4 input A of the two-input NAND gate (Y = A·B); unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V. |
| 13 | 4B | input | Gate 4 input B of the two-input NAND gate (Y = A·B); unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V. |
| 14 | VCC | power_in | Supply voltage, recommended 4.5 V to 5.5 V; absolute maximum 7 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | | 7 | V | | 3 |
| Input voltage | VI | -0.5 | | | V | Max printed as VCC + 0.5 V | 3 |
| Output voltage | VO | -0.5 | | | V | Max printed as VCC + 0.5 V | 3 |
| Input clamp current | IIK | -20 | | 20 | mA | VI < 0 or VI > VCC | 3 |
| Output clamp current | IOK | -20 | | 20 | mA | VO < 0 or VO > VCC | 3 |
| Continuous output current | IO | -50 | | 50 | mA | VO = 0 to VCC | 3 |
| Continuous current through VCC or GND | | -200 | | 200 | mA | | 3 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 3 |
| Supply voltage | VCC | 4.5 | | 5.5 | V | | 3 |
| High-level input voltage | VIH | 2 | | | V | | 3 |
| Low-level input voltage | VIL | | | 0.8 | V | | 3 |
| Input voltage | VI | 0 | | | V | Max printed as VCC | 3 |
| Output voltage | VO | 0 | | | V | Max printed as VCC | 3 |
| High-level output current | IOH | | | -24 | mA | | 3 |
| Low-level output current | IOL | | | 24 | mA | | 3 |
| Input transition rise or fall rate | Δt/Δv | | | 8 | ns/V | | 3 |
| Operating free-air temperature | TA | -40 | | 105 | °C | | 3 |
| Junction-to-ambient thermal resistance (D, SOIC-14) | RθJA | | 86 | | °C/W | | 3 |
| High-level output voltage | VOH | 4.4 | 4.49 | | V | IOH = -50 µA; VCC = 4.5 V; TA = 25°C | 4 |
| High-level output voltage | VOH | 4.4 | | | V | IOH = -50 µA; VCC = 4.5 V; full operating temperature range | 4 |
| High-level output voltage | VOH | 5.4 | 5.49 | | V | IOH = -50 µA; VCC = 5.5 V; TA = 25°C | 4 |
| High-level output voltage | VOH | 5.4 | | | V | IOH = -50 µA; VCC = 5.5 V; full operating temperature range | 4 |
| High-level output voltage | VOH | 3.86 | | | V | IOH = -24 mA; VCC = 4.5 V; TA = 25°C | 4 |
| High-level output voltage | VOH | 3.7 | | | V | IOH = -24 mA; VCC = 4.5 V; full operating temperature range | 4 |
| High-level output voltage | VOH | 4.86 | | | V | IOH = -24 mA; VCC = 5.5 V; TA = 25°C | 4 |
| High-level output voltage | VOH | 4.7 | | | V | IOH = -24 mA; VCC = 5.5 V; full operating temperature range | 4 |
| Low-level output voltage | VOL | | 0.001 | 0.1 | V | IOL = 50 µA; VCC = 4.5 V; TA = 25°C | 4 |
| Low-level output voltage | VOL | | | 0.1 | V | IOL = 50 µA; VCC = 4.5 V; full operating temperature range | 4 |
| Low-level output voltage | VOL | | 0.36 | 0.5 | V | IOL = 24 mA; VCC = 4.5 V | 4 |
| Input leakage current | II | -0.1 | | 0.1 | µA | VI = VCC or GND; VCC = 5.5 V; TA = 25°C | 4 |
| Input leakage current | II | -1 | | 1 | µA | VI = VCC or GND; VCC = 5.5 V; full operating temperature range | 4 |
| Supply current | ICC | | 2 | 40 | µA | VI = VCC or GND, IO = 0; VCC = 5.5 V | 4 |
| Additional supply current per input at TTL level | ΔICC | | 0.6 | 1.6 | mA | One input at 3.4 V, other inputs at GND or VCC; VCC = 5.5 V | 4 |
| Propagation delay time, low-to-high-level output (A or B to Y) | tPLH | 1.5 | 5.5 | 9 | ns | VCC = 5 V ± 0.5 V; TA = 25°C; see Figure 4-1 | 4 |
| Propagation delay time, low-to-high-level output (A or B to Y) | tPLH | 1 | | 9.5 | ns | VCC = 5 V ± 0.5 V; full operating temperature range; see Figure 4-1 | 4 |
| Propagation delay time, high-to-low-level output (A or B to Y) | tPHL | 1.5 | 4 | 7 | ns | VCC = 5 V ± 0.5 V; TA = 25°C; see Figure 4-1 | 4 |
| Propagation delay time, high-to-low-level output (A or B to Y) | tPHL | 1 | | 8 | ns | VCC = 5 V ± 0.5 V; full operating temperature range; see Figure 4-1 | 4 |
| Input capacitance | Ci | | 2.6 | | pF | VI = VCC or GND; VCC = 5 V | 4 |
| Power dissipation capacitance | Cpd | | 40 | | pF | CL = 50 pF, f = 1 MHz; VCC = 5 V; TA = 25°C | 4 |
## CAD (KiCad official)
- Symbol: `SN74ACT00TDRQ1`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `sn74act00tdrq1-etched.step` / `sn74act00tdrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74act00tdrq1.step` / `sn74act00tdrq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74act00-q1) (23 pp, sha256 `d2227c484855ddfb`, retrieved 2026-10-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74act00tdrq1-datasheet.pdf)