component

SN74ACT00N

Public Made by Adom

by adom

Texas Instruments Gates, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icssn74act00nfactory-2.0.0extractor-text

Verified SN74ACT00N

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 14 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: SN74ACT00N · PDIP-14 · 14 pins
  • ✓copper: 14 copper pads, none touching another net
  • ✓datasheet: all 14 pin names found in the 22-page datasheet
  • ✓distributor: lcsc C2871173, digikey 2156-SN74ACT00N-ND, mouser 595-SN74ACT00N
  • ✓family: DIP-14_W7.62mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-rv63qzb4/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 14 pins = 14 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 14 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ sn74act00n.kicad_sym✓ sn74act00n.kicad_mod✓ sn74act00n.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 10h ago
viewers sn74act00n: viewers · Ray 10h ago
package.json Publish 0.1.0 · Ray 10h ago
page.json Set visibility: public · Ray 10h ago
README.md Publish 0.1.0 · Ray 10h ago
sn74act00n-etched.glb Publish 0.1.0 · Ray 10h ago
sn74act00n-etched.step sn74act00n: factory component page (tier=mfr) · Ray 10h ago
sn74act00n-hero.glb sn74act00n: hero GLB from the etched model (keeps the MPN mark) · Ray 10h ago
sn74act00n-hero.overlay.json Publish 0.1.0 · Ray 10h ago
sn74act00n.glb Publish 0.1.0 · Ray 10h ago
sn74act00n.kicad_mod Publish 0.1.0 · Ray 10h ago
sn74act00n.kicad_sym Publish 0.1.0 · Ray 10h ago
sn74act00n.lbr Publish 0.1.0 · Ray 10h ago
sn74act00n.step Publish 0.1.0 · Ray 10h ago
verification.json Verified: Published by the parts factory: tier mfr, 14 pins · Ray 10h ago

SN74ACT00N

Texas Instruments · Gates · PDIP-14

SN74ACT00N from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input A of NAND gate 1; TTL-voltage compatible with input voltage range 0 V to VCC, and unused inputs must be held at VCC or GND.
2 1B input Data input B of NAND gate 1; TTL-voltage compatible with input voltage range 0 V to VCC, and unused inputs must be held at VCC or GND.
3 1Y output Output of NAND gate 1 (Y = A·B), rated for −24 mA high-level and 24 mA low-level output current.
4 2A input Data input A of NAND gate 2; TTL-voltage compatible with input voltage range 0 V to VCC, and unused inputs must be held at VCC or GND.
5 2B input Data input B of NAND gate 2; TTL-voltage compatible with input voltage range 0 V to VCC, and unused inputs must be held at VCC or GND.
6 2Y output Output of NAND gate 2 (Y = A·B), rated for −24 mA high-level and 24 mA low-level output current.
7 GND power_in Ground reference for the device; inputs and outputs are specified relative to GND and VCC.
8 3Y output Output of NAND gate 3 (Y = A·B), rated for −24 mA high-level and 24 mA low-level output current.
9 3A input Data input A of NAND gate 3; TTL-voltage compatible with input voltage range 0 V to VCC, and unused inputs must be held at VCC or GND.
10 3B input Data input B of NAND gate 3; TTL-voltage compatible with input voltage range 0 V to VCC, and unused inputs must be held at VCC or GND.
11 4Y output Output of NAND gate 4 (Y = A·B), rated for −24 mA high-level and 24 mA low-level output current.
12 4A input Data input A of NAND gate 4; TTL-voltage compatible with input voltage range 0 V to VCC, and unused inputs must be held at VCC or GND.
13 4B input Data input B of NAND gate 4; TTL-voltage compatible with input voltage range 0 V to VCC, and unused inputs must be held at VCC or GND.
14 VCC power_in Positive supply; recommended operating range is 4.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-level output voltage, IOH = −50 µA, VCC = 4.5 V VOH 4.4 V IOH = −50 µA; VCC = 4.5 V 3
High-level output voltage, IOH = −50 µA, VCC = 5.5 V VOH 5.4 V IOH = −50 µA; VCC = 5.5 V 3
High-level output voltage, IOH = −24 mA, VCC = 4.5 V VOH 3.76 V IOH = −24 mA; VCC = 4.5 V 3
High-level output voltage, IOH = −24 mA, VCC = 5.5 V VOH 4.76 V IOH = −24 mA; VCC = 5.5 V 3
Low-level output voltage, IOL = 50 µA, VCC = 4.5 V VOL 0.1 V IOL = 50 µA; VCC = 4.5 V 3
Low-level output voltage, IOL = 50 µA, VCC = 5.5 V VOL 0.1 V IOL = 50 µA; VCC = 5.5 V 3
Low-level output voltage, IOL = 24 mA, VCC = 4.5 V VOL 0.44 V IOL = 24 mA; VCC = 4.5 V 3
Low-level output voltage, IOL = 24 mA, VCC = 5.5 V VOL 0.44 V IOL = 24 mA; VCC = 5.5 V 3
Input current II -1 1 µA VI = VCC or GND; VCC = 5.5 V 3
Quiescent supply current ICC 20 µA VI = VCC or GND, IO = 0; VCC = 5.5 V 3
Increase in supply current per input at 3.4 V ΔICC 1.5 mA One input at 3.4 V, other inputs at GND or VCC; VCC = 5.5 V 3
Propagation delay time, low-to-high level output (A or B to Y) tPLH 1 9.5 ns VCC = 5 V ± 0.5 V; see Figure 1 3
Propagation delay time, high-to-low level output (A or B to Y) tPHL 1 8 ns VCC = 5 V ± 0.5 V; see Figure 1 3
Supply voltage (recommended) VCC 4.5 5.5 V 2
High-level input voltage VIH 2 V 2
Low-level input voltage VIL 0.8 V 2
Input voltage VI 0 V Printed maximum is VCC 2
Output voltage VO 0 V Printed maximum is VCC 2
High-level output current IOH -24 mA 2
Low-level output current IOL 24 mA 2
Input transition rise or fall rate Δt/Δv 8 ns/V 2
Operating free-air temperature TA -40 85 °C SN74ACT00 2
Supply voltage VCC -0.5 7 V 2
Input voltage range VI -0.5 V See Note 1; printed maximum is VCC + 0.5 V 2
Output voltage range VO -0.5 V See Note 1; printed maximum is VCC + 0.5 V 2
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 2
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 2
Continuous output current IO -50 50 mA VO = 0 to VCC 2
Continuous current through VCC or GND -200 200 mA 2
Storage temperature range Tstg -65 150 °C 2
Package thermal impedance, N package θJA 80 °C/W N package; calculated per JESD 51-7 2

CAD (KiCad official)

  • Symbol: SN74ACT00N
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: PDIP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74act00n-etched.step / sn74act00n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74act00n.step / sn74act00n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (22 pp, sha256 405c050213bdd4d3, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF