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Initial commit: component/sn74act00d

Ray ·ed320852f5 ·1d ago
2 files changed +288
README.mdadded+51
@@ -0,0 +1,51 @@+# SN74ACT00D++**Texas Instruments** · Logic Gates · SOIC-14++SN74ACT00D from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | Channel 1 input A of NAND gate 1 (Y = A·B for positive logic). |+| 2 | 1B | input | Channel 1 input B of NAND gate 1 (Y = A·B for positive logic). |+| 3 | 1Y | output | Channel 1 output Y of NAND gate 1. |+| 4 | 2A | input | Channel 2 input A of NAND gate 2 (Y = A·B for positive logic). |+| 5 | 2B | input | Channel 2 input B of NAND gate 2 (Y = A·B for positive logic). |+| 6 | 2Y | output | Channel 2 output Y of NAND gate 2. |+| 7 | GND | power_in | Ground reference for the device. |+| 8 | 3Y | output | Channel 3 output Y of NAND gate 3. |+| 9 | 3A | input | Channel 3 input A of NAND gate 3 (Y = A·B for positive logic). |+| 10 | 3B | input | Channel 3 input B of NAND gate 3 (Y = A·B for positive logic). |+| 11 | 4Y | output | Channel 4 output Y of NAND gate 4. |+| 12 | 4A | input | Channel 4 input A of NAND gate 4 (Y = A·B for positive logic). |+| 13 | 4B | input | Channel 4 input B of NAND gate 4 (Y = A·B for positive logic). |+| 14 | VCC | power_in | Positive supply; recommended operating range is 4.5 V to 5.5 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `SN74ACT00D`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)+- 3D model files: `sn74act00d-etched.step` / `sn74act00d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74act00d.step` / `sn74act00d.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn54act00) (37 pp, sha256 `667a256539439088`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74act00d-datasheet.pdf)
page.jsonadded+237
@@ -0,0 +1,237 @@+{+  "slug": "sn74act00d",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "sn74act00d",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "sn74act00d.kicad_sym",+    "sn74act00d.kicad_mod",+    "sn74act00d.glb",+    "sn74act00d.step",+    "sn74act00d.lbr",+    "docs/hero.png",+    "docs/sn74act00d-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "sn74act00d-hero.glb",+    "sn74act00d-hero.overlay.json"+  ],+  "component": {+    "mpn": "SN74ACT00D",+    "manufacturer": "Texas Instruments",+    "package": "SOIC-14",+    "pin_count": 14,+    "category": "Logic",+    "subcategory": "Logic Gates",+    "datasheet": "https://www.ti.com/cn/lit/gpn/sn54act00",+    "parts": {+      "symbol": "sn74act00d.kicad_sym",+      "footprint": "sn74act00d.kicad_mod",+      "model_3d": "sn74act00d-hero.glb",+      "model_3d_plain": "sn74act00d.glb",+      "model_3d_step": "sn74act00d-etched.step",+      "model_3d_step_plain": "sn74act00d.step",+      "lbr": "sn74act00d.lbr"+    },+    "distributor_links": {+      "lcsc": "C2869090",+      "digikey": "2156-SN74ACT00D-ND",+      "mouser": "595-SN74ACT00D"+    },+    "distributor_check": {+      "checked_at": "2026-10-08T20:17:44Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "2156-SN74ACT00D-ND",+        "status": "found",+        "lifecycle": "Obsolete"+      },+      "mouser": {+        "pn": "595-SN74ACT00D",+        "status": "found",+        "lifecycle": "Obsolete"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "1A",+        "type": "input",+        "description": "Channel 1 input A of NAND gate 1 (Y = A·B for positive logic)."+      },+      {+        "number": "2",+        "name": "1B",+        "type": "input",+        "description": "Channel 1 input B of NAND gate 1 (Y = A·B for positive logic)."+      },+      {+        "number": "3",+        "name": "1Y",+        "type": "output",+        "description": "Channel 1 output Y of NAND gate 1."+      },+      {+        "number": "4",+        "name": "2A",+        "type": "input",+        "description": "Channel 2 input A of NAND gate 2 (Y = A·B for positive logic)."+      },+      {+        "number": "5",+        "name": "2B",+        "type": "input",+        "description": "Channel 2 input B of NAND gate 2 (Y = A·B for positive logic)."+      },+      {+        "number": "6",+        "name": "2Y",+        "type": "output",+        "description": "Channel 2 output Y of NAND gate 2."+      },+      {+        "number": "7",+        "name": "GND",+        "type": "power_in",+        "description": "Ground reference for the device."+      },+      {+        "number": "8",+        "name": "3Y",+        "type": "output",+        "description": "Channel 3 output Y of NAND gate 3."+      },+      {+        "number": "9",+        "name": "3A",+        "type": "input",+        "description": "Channel 3 input A of NAND gate 3 (Y = A·B for positive logic)."+      },+      {+        "number": "10",+        "name": "3B",+        "type": "input",+        "description": "Channel 3 input B of NAND gate 3 (Y = A·B for positive logic)."+      },+      {+        "number": "11",+        "name": "4Y",+        "type": "output",+        "description": "Channel 4 output Y of NAND gate 4."+      },+      {+        "number": "12",+        "name": "4A",+        "type": "input",+        "description": "Channel 4 input A of NAND gate 4 (Y = A·B for positive logic)."+      },+      {+        "number": "13",+        "name": "4B",+        "type": "input",+        "description": "Channel 4 input B of NAND gate 4 (Y = A·B for positive logic)."+      },+      {+        "number": "14",+        "name": "VCC",+        "type": "power_in",+        "description": "Positive supply; recommended operating range is 4.5 V to 5.5 V."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-5-5",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "extractor flagged: Table 3-1 on page 3 lists the direction for 3A, 3Y, 4A and 4Y inconsistently: 3A and 4A are marked O; Pin 14 description cites the supply range from page 5 rather than page 3. The datasheet gives no per; Package-variant note: the SN74ACT00D orderable part is marked Obsolete in the TI package addendum (p"+        ],+        "pages_sent": 37,+        "cost_usd": 0.11,+        "at": "2026-10-08T20:17:15"+      },+      "datasheet": {+        "url": "https://www.ti.com/cn/lit/gpn/sn54act00",+        "pages": 37,+        "sha256": "667a256539439088",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    },+    "models_3d": [+      {+        "file": "sn74act00d.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          6,+          8.7,+          1.75+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "sn74act00d-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          6,+          8.7,+          1.75+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "b6594239168013b508ca967cd3ebd9cac9ea705d4dbab44853153495796620b0",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file