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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

SN74AC374PWR

Texas Instruments · Flip Flops · TSSOP-20

SN74AC374PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OE	input	Output enable input; low enables 3-state outputs to normal logic levels, high places outputs in high-impedance state.
2	1Q	tri_state	3-state output Q of flip-flop 1; driven to logic level when OE is low, high-impedance when OE is high.
3	1D	input	Data input D for flip-flop 1; captured on rising edge of clock when OE is low.
4	2D	input	Data input D for flip-flop 2; captured on rising edge of clock when OE is low.
5	2Q	tri_state	3-state output Q of flip-flop 2; driven to logic level when OE is low, high-impedance when OE is high.
6	3Q	tri_state	3-state output Q of flip-flop 3; driven to logic level when OE is low, high-impedance when OE is high.
7	3D	input	Data input D for flip-flop 3; captured on rising edge of clock when OE is low.
8	4D	input	Data input D for flip-flop 4; captured on rising edge of clock when OE is low.
9	4Q	tri_state	3-state output Q of flip-flop 4; driven to logic level when OE is low, high-impedance when OE is high.
10	GND	power_in	Ground; reference voltage for the device.
11	CLK	input	Clock input; positive edge-triggered for loading D inputs into flip-flops, maximum frequency 100 MHz at VCC = 5V.
12	5Q	tri_state	3-state output Q of flip-flop 5; driven to logic level when OE is low, high-impedance when OE is high.
13	5D	input	Data input D for flip-flop 5; captured on rising edge of clock when OE is low.
14	6D	input	Data input D for flip-flop 6; captured on rising edge of clock when OE is low.
15	6Q	tri_state	3-state output Q of flip-flop 6; driven to logic level when OE is low, high-impedance when OE is high.
16	7Q	tri_state	3-state output Q of flip-flop 7; driven to logic level when OE is low, high-impedance when OE is high.
17	7D	input	Data input D for flip-flop 7; captured on rising edge of clock when OE is low.
18	8D	input	Data input D for flip-flop 8; captured on rising edge of clock when OE is low.
19	8Q	tri_state	3-state output Q of flip-flop 8; driven to logic level when OE is low, high-impedance when OE is high.
20	VCC	power_in	Positive power supply voltage; operating range 2V to 6V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-20
Category	Logic
Pins	20

CAD (KiCad official)

Symbol: SN74AC374PWR
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model files: sn74ac374pwr-etched.step / sn74ac374pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ac374pwr.step / sn74ac374pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (32 pp, sha256 63b2ea5df6afbd25, retrieved 2026-09-24, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF