# SN74AC373N

**Texas Instruments** · Latches · PDIP-20

SN74AC373N from Texas Instruments, in a PDIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Output enable: when OE is high the eight Q outputs go to the high-impedance state, and OE must be tied to VCC through a pullup resistor for the specified high-impedance state during power up or power down. |
| 2 | 1Q | tri_state | Three-state noninverting latch output 1, which follows 1D while LE is high and holds its latched level when LE goes low. |
| 3 | 1D | input | Data input to latch 1, which is sampled while LE is high and must meet the setup and hold times referenced to the falling edge of LE. |
| 4 | 2D | input | Data input to latch 2, which is sampled while LE is high and must meet the setup and hold times referenced to the falling edge of LE. |
| 5 | 2Q | tri_state | Three-state noninverting latch output 2, which follows 2D while LE is high and holds its latched level when LE goes low. |
| 6 | 3Q | tri_state | Three-state noninverting latch output 3, which follows 3D while LE is high and holds its latched level when LE goes low. |
| 7 | 3D | input | Data input to latch 3, which is sampled while LE is high and must meet the setup and hold times referenced to the falling edge of LE. |
| 8 | 4D | input | Data input to latch 4, which is sampled while LE is high and must meet the setup and hold times referenced to the falling edge of LE. |
| 9 | 4Q | tri_state | Three-state noninverting latch output 4, which follows 4D while LE is high and holds its latched level when LE goes low. |
| 10 | GND | power_in | Ground pin. |
| 11 | LE | input | Latch enable: when LE is high the Q outputs follow the D inputs, and when LE is taken low the Q outputs latch the logic levels present at the D inputs. |
| 12 | 5Q | tri_state | Three-state noninverting latch output 5, which follows 5D while LE is high and holds its latched level when LE goes low. |
| 13 | 5D | input | Data input to latch 5, which is sampled while LE is high and must meet the setup and hold times referenced to the falling edge of LE. |
| 14 | 6D | input | Data input to latch 6, which is sampled while LE is high and must meet the setup and hold times referenced to the falling edge of LE. |
| 15 | 6Q | tri_state | Three-state noninverting latch output 6, which follows 6D while LE is high and holds its latched level when LE goes low. |
| 16 | 7Q | tri_state | Three-state noninverting latch output 7, which follows 7D while LE is high and holds its latched level when LE goes low. |
| 17 | 7D | input | Data input to latch 7, which is sampled while LE is high and must meet the setup and hold times referenced to the falling edge of LE. |
| 18 | 8D | input | Data input to latch 8, which is sampled while LE is high and must meet the setup and hold times referenced to the falling edge of LE. |
| 19 | 8Q | tri_state | Three-state noninverting latch output 8, which follows 8D while LE is high and holds its latched level when LE goes low. |
| 20 | VCC | power_in | Power supply pin; the recommended supply range is 2 V to 6 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-20 |
| Category | Logic |
| Pins | 20 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-level output voltage (IOH = -50 μA) | VOH | 2.9 |  |  | V | IOH = -50 μA, VCC = 3 V | 5 |
| High-level output voltage (IOH = -50 μA) | VOH | 4.4 |  |  | V | IOH = -50 μA, VCC = 4.5 V | 5 |
| High-level output voltage (IOH = -50 μA) | VOH | 5.4 |  |  | V | IOH = -50 μA, VCC = 5.5 V | 5 |
| High-level output voltage (IOH = -12 mA) | VOH | 2.46 |  |  | V | IOH = -12 mA, VCC = 3 V | 5 |
| High-level output voltage (IOH = -24 mA) | VOH | 3.76 |  |  | V | IOH = -24 mA, VCC = 4.5 V | 5 |
| High-level output voltage (IOH = -24 mA) | VOH | 4.76 |  |  | V | IOH = -24 mA, VCC = 5.5 V | 5 |
| Low-level output voltage (IOL = 50 μA) | VOL |  |  | 0.1 | V | IOL = 50 μA, VCC = 3 V | 5 |
| Low-level output voltage (IOL = 12 mA) | VOL |  |  | 0.44 | V | IOL = 12 mA, VCC = 3 V | 5 |
| Low-level output voltage (IOL = 24 mA) | VOL |  |  | 0.44 | V | IOL = 24 mA, VCC = 4.5 V | 5 |
| Input current | II | -1 |  | 1 | μA | VI = VCC or GND, VCC = 5.5 V | 5 |
| Off-state (high-impedance) output current | IOZ | -2.5 |  | 2.5 | μA | VO = VCC or GND, VCC = 5.5 V | 5 |
| Supply current | ICC |  |  | 40 | μA | VI = VCC or GND, IO = 0, VCC = 5.5 V | 5 |
| Pulse duration, LE high | tw | 6 |  |  | ns | VCC = 3.3 V ± 0.3 V | 5 |
| Setup time, data before LE↓ | tsu | 6 |  |  | ns | VCC = 3.3 V ± 0.3 V | 5 |
| Hold time, data after LE↓ | th | 1 |  |  | ns | VCC = 3.3 V ± 0.3 V | 5 |
| Pulse duration, LE high | tw | 4.5 |  |  | ns | VCC = 5 V ± 0.5 V | 5 |
| Setup time, data before LE↓ | tsu | 4.5 |  |  | ns | VCC = 5 V ± 0.5 V | 5 |
| Propagation delay low-to-high, D to Q | tPLH | 1.5 | 10 | 15 | ns | D to Q, VCC = 3.3 V ± 0.3 V | 6 |
| Propagation delay high-to-low, D to Q | tPHL | 1.5 | 9.5 | 14.5 | ns | D to Q, VCC = 3.3 V ± 0.3 V | 6 |
| Propagation delay low-to-high, LE to Q | tPLH | 1.5 | 10 | 15 | ns | LE to Q, VCC = 3.3 V ± 0.3 V | 6 |
| Propagation delay high-to-low, LE to Q | tPHL | 1.5 | 9.5 | 14 | ns | LE to Q, VCC = 3.3 V ± 0.3 V | 6 |
| Output enable time high, OE to Q | tPZH | 1 | 9 | 13 | ns | OE to Q, VCC = 3.3 V ± 0.3 V | 6 |
| Output enable time low, OE to Q | tPZL | 1 | 8.5 | 13 | ns | OE to Q, VCC = 3.3 V ± 0.3 V | 6 |
| Output disable time high, OE to Q | tPHZ | 1 | 10 | 14.5 | ns | OE to Q, VCC = 3.3 V ± 0.3 V | 6 |
| Output disable time low, OE to Q | tPLZ | 1 | 8 | 12.5 | ns | OE to Q, VCC = 3.3 V ± 0.3 V | 6 |
| Propagation delay low-to-high, D to Q | tPLH | 1.5 | 7 | 10.5 | ns | D to Q, VCC = 5 V ± 0.5 V | 6 |
| Propagation delay high-to-low, D to Q | tPHL | 1.5 | 7 | 10.5 | ns | D to Q, VCC = 5 V ± 0.5 V | 6 |
| Propagation delay low-to-high, LE to Q | tPLH | 1.5 | 7.5 | 10.5 | ns | LE to Q, VCC = 5 V ± 0.5 V | 6 |
| Propagation delay high-to-low, LE to Q | tPHL | 1.5 | 7 | 10.5 | ns | LE to Q, VCC = 5 V ± 0.5 V | 6 |
| Output enable time high, OE to Q | tPZH | 1 | 7 | 9.5 | ns | OE to Q, VCC = 5 V ± 0.5 V | 6 |
| Output enable time low, OE to Q | tPZL | 1 | 6.5 | 9.5 | ns | OE to Q, VCC = 5 V ± 0.5 V | 6 |
| Output disable time high, OE to Q | tPHZ | 1 | 8 | 12.5 | ns | OE to Q, VCC = 5 V ± 0.5 V | 6 |
| Output disable time low, OE to Q | tPLZ | 1 | 6.5 | 10 | ns | OE to Q, VCC = 5 V ± 0.5 V | 6 |
| Supply voltage | VCC | 2 |  | 6 | V |  | 4 |
| High-level input voltage | VIH | 2.1 |  |  | V | VCC = 3 V | 4 |
| High-level input voltage | VIH | 3.15 |  |  | V | VCC = 4.5 V | 4 |
| High-level input voltage | VIH | 3.85 |  |  | V | VCC = 5.5 V | 4 |
| Low-level input voltage | VIL |  |  | 0.9 | V | VCC = 3 V | 4 |
| Low-level input voltage | VIL |  |  | 1.35 | V | VCC = 4.5 V | 4 |
| Low-level input voltage | VIL |  |  | 1.65 | V | VCC = 5.5 V | 4 |
| Input voltage | VI | 0 |  |  | V | maximum printed as VCC | 4 |
| High-level output current | IOH | -12 |  |  | mA | VCC = 3 V | 4 |
| High-level output current | IOH | -24 |  |  | mA | VCC = 4.5 V | 4 |
| Low-level output current | IOL |  |  | 12 | mA | VCC = 3 V | 4 |
| Low-level output current | IOL |  |  | 24 | mA | VCC = 4.5 V | 4 |
| Input transition rise or fall rate | Δt/Δv |  |  | 8 | ns/V |  | 4 |
| Operating free-air temperature | TA | -40 |  | 85 | °C | SN74AC373 | 4 |
| Supply voltage range | VCC | -0.5 |  | 7 | V |  | 4 |
| Input clamp current | IIK | -20 |  | 20 | mA | VI < 0 or VI > VCC | 4 |
| Output clamp current | IOK | -20 |  | 20 | mA | VO < 0 or VO > VCC | 4 |
| Continuous output current | IO | -50 |  | 50 | mA | VO = 0 to VCC | 4 |
| Continuous current through VCC or GND |  | -200 |  | 200 | mA |  | 4 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 4 |
| Junction-to-ambient thermal resistance | RθJA |  | 69 |  | °C/W | N (PDIP) package, 20 pins | 5 |

## CAD (KiCad official)

- Symbol: `SN74AC373N`
- Footprint: `Package_DIP:DIP-20_W7.62mm`
- 3D model: PDIP-20 (KiCad packages3D, STEP)
- 3D model files: `sn74ac373n-etched.step` / `sn74ac373n-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ac373n.step` / `sn74ac373n.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74ac373) (32 pp, sha256 `bcc4551bd99a97ba`, retrieved 2026-10-16, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74ac373n-datasheet.pdf)