component
SN74AC32PWR
Public Made by Adomby adom
Texas Instruments Logic ICs, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74AC32PWR
Texas Instruments · Logic ICs · TSSOP-14
SN74AC32PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1 input A of the 2-input OR gate; unused inputs must be tied to VCC or GND. |
| 2 | 1B | input | Gate 1 input B of the 2-input OR gate; unused inputs must be tied to VCC or GND. |
| 3 | 1Y | output | Gate 1 output, Y = A + B. |
| 4 | 2A | input | Gate 2 input A of the 2-input OR gate; unused inputs must be tied to VCC or GND. |
| 5 | 2B | input | Gate 2 input B of the 2-input OR gate; unused inputs must be tied to VCC or GND. |
| 6 | 2Y | output | Gate 2 output, Y = A + B. |
| 7 | GND | power_in | Ground pin. |
| 8 | 3Y | output | Gate 3 output, Y = A + B. |
| 9 | 3A | input | Gate 3 input A of the 2-input OR gate; unused inputs must be tied to VCC or GND. |
| 10 | 3B | input | Gate 3 input B of the 2-input OR gate; unused inputs must be tied to VCC or GND. |
| 11 | 4Y | output | Gate 4 output, Y = A + B. |
| 12 | 4A | input | Gate 4 input A of the 2-input OR gate; unused inputs must be tied to VCC or GND. |
| 13 | 4B | input | Gate 4 input B of the 2-input OR gate; unused inputs must be tied to VCC or GND. |
| 14 | VCC | power_in | Power pin; supply voltage 2 V to 6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic ICs |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VCC | -0.5 | 7 | V | 5 | ||
| Input voltage range | VI | -0.5 | V | max printed as VCC + 0.5 V | 5 | ||
| Output voltage range | VO | -0.5 | V | max printed as VCC + 0.5 V | 5 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0 or VI > VCC | 5 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VCC | 5 | |
| Continuous output current | IO | -50 | 50 | mA | VO = 0 to VCC | 5 | |
| Continuous current through VCC or GND | IO | -200 | 200 | mA | 5 | ||
| Storage temperature range | Tstg | -65 | 150 | °C | 5 | ||
| Supply voltage | VCC | 2 | 6 | V | 5 | ||
| High-level input voltage | VIH | 2.1 | V | VCC = 3 V | 5 | ||
| High-level input voltage | VIH | 3.15 | V | VCC = 4.5 V | 5 | ||
| High-level input voltage | VIH | 3.85 | V | VCC = 5.5 V | 5 | ||
| Low-level input voltage | VIL | 0.9 | V | VCC = 3 V | 5 | ||
| Low-level input voltage | VIL | 1.35 | V | VCC = 4.5 V | 5 | ||
| Low-level input voltage | VIL | 1.65 | V | VCC = 5.5 V | 5 | ||
| Input voltage | VI | 0 | V | max = VCC | 5 | ||
| Output voltage | VO | 0 | V | max = VCC | 5 | ||
| High-level output current | IOH | -12 | mA | VCC = 3 V | 5 | ||
| High-level output current | IOH | -24 | mA | VCC = 4.5 V | 5 | ||
| Low-level output current | IOL | 12 | mA | VCC = 3 V | 5 | ||
| Low-level output current | IOL | 24 | mA | VCC = 4.5 V | 5 | ||
| Input transition rise or fall rate | ∆t/∆v | 8 | ns/V | 5 | |||
| Operating free-air temperature | TA | -55 | 125 | °C | 5 | ||
| High-level output voltage | VOH | 2.9 | V | IOH = -50µA, VCC = 3 V | 6 | ||
| High-level output voltage | VOH | 4.4 | V | IOH = -50µA, VCC = 4.5 V | 6 | ||
| High-level output voltage | VOH | 5.4 | V | IOH = -50µA, VCC = 5.5 V | 6 | ||
| High-level output voltage | VOH | 2.4 | V | IOH = -12mA, VCC = 3 V | 6 | ||
| High-level output voltage | VOH | 3.7 | V | IOH = -24mA, VCC = 4.5 V | 6 | ||
| High-level output voltage | VOH | 4.7 | V | IOH = -24mA, VCC = 5.5 V | 6 | ||
| Low-level output voltage | VOL | 0.002 | 0.1 | V | IOL = 50 µA, VCC = 3 V, TA = 25°C typ | 6 | |
| Low-level output voltage | VOL | 0.001 | 0.1 | V | IOL = 50 µA, VCC = 4.5 V, TA = 25°C typ | 6 | |
| Low-level output voltage | VOL | 0.36 | 0.5 | V | IOL = 12mA, VCC = 3 V, TA = 25°C typ | 6 | |
| Input current | II | -1 | 1 | µA | A or B ports, VI = VCC or GND, VCC = 5.5 V | 6 | |
| Quiescent supply current | ICC | 2 | 40 | µA | VI = VCC or GND, IO = 0, VCC = 5.5 V | 6 | |
| Propagation delay low-to-high, VCC = 3.3V ± 0.3V | tPLH | 1 | 7 | 12 | ns | A or B to Y, VCC = 3.3 V ± 0.3 V | 7 |
| Propagation delay high-to-low, VCC = 3.3V ± 0.3V | tPHL | 1 | 7 | 11.5 | ns | A or B to Y, VCC = 3.3 V ± 0.3 V | 7 |
| Propagation delay low-to-high, VCC = 5V ± 0.5V | tPLH | 1 | 5.5 | 9 | ns | A or B to Y, VCC = 5 V ± 0.5 V | 7 |
| Propagation delay high-to-low, VCC = 5V ± 0.5V | tPHL | 1 | 5 | 8.5 | ns | A or B to Y, VCC = 5 V ± 0.5 V | 7 |
| Junction-to-ambient thermal resistance (PW, TSSOP) | RθJA | 145.7 | °C/W | PW (TSSOP) 14-pin package | 6 |
CAD (KiCad official)
- Symbol:
SN74AC32PWR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74ac32pwr-etched.step/sn74ac32pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ac32pwr.step/sn74ac32pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (39 pp, sha256
812fdbbf4f81846e, retrieved 2026-10-17, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74AC32PWR
**Texas Instruments** · Logic ICs · TSSOP-14
SN74AC32PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1 input A of the 2-input OR gate; unused inputs must be tied to VCC or GND. |
| 2 | 1B | input | Gate 1 input B of the 2-input OR gate; unused inputs must be tied to VCC or GND. |
| 3 | 1Y | output | Gate 1 output, Y = A + B. |
| 4 | 2A | input | Gate 2 input A of the 2-input OR gate; unused inputs must be tied to VCC or GND. |
| 5 | 2B | input | Gate 2 input B of the 2-input OR gate; unused inputs must be tied to VCC or GND. |
| 6 | 2Y | output | Gate 2 output, Y = A + B. |
| 7 | GND | power_in | Ground pin. |
| 8 | 3Y | output | Gate 3 output, Y = A + B. |
| 9 | 3A | input | Gate 3 input A of the 2-input OR gate; unused inputs must be tied to VCC or GND. |
| 10 | 3B | input | Gate 3 input B of the 2-input OR gate; unused inputs must be tied to VCC or GND. |
| 11 | 4Y | output | Gate 4 output, Y = A + B. |
| 12 | 4A | input | Gate 4 input A of the 2-input OR gate; unused inputs must be tied to VCC or GND. |
| 13 | 4B | input | Gate 4 input B of the 2-input OR gate; unused inputs must be tied to VCC or GND. |
| 14 | VCC | power_in | Power pin; supply voltage 2 V to 6 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic ICs |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VCC | -0.5 | | 7 | V | | 5 |
| Input voltage range | VI | -0.5 | | | V | max printed as VCC + 0.5 V | 5 |
| Output voltage range | VO | -0.5 | | | V | max printed as VCC + 0.5 V | 5 |
| Input clamp current | IIK | -20 | | 20 | mA | VI < 0 or VI > VCC | 5 |
| Output clamp current | IOK | -20 | | 20 | mA | VO < 0 or VO > VCC | 5 |
| Continuous output current | IO | -50 | | 50 | mA | VO = 0 to VCC | 5 |
| Continuous current through VCC or GND | IO | -200 | | 200 | mA | | 5 |
| Storage temperature range | Tstg | -65 | | 150 | °C | | 5 |
| Supply voltage | VCC | 2 | | 6 | V | | 5 |
| High-level input voltage | VIH | 2.1 | | | V | VCC = 3 V | 5 |
| High-level input voltage | VIH | 3.15 | | | V | VCC = 4.5 V | 5 |
| High-level input voltage | VIH | 3.85 | | | V | VCC = 5.5 V | 5 |
| Low-level input voltage | VIL | | | 0.9 | V | VCC = 3 V | 5 |
| Low-level input voltage | VIL | | | 1.35 | V | VCC = 4.5 V | 5 |
| Low-level input voltage | VIL | | | 1.65 | V | VCC = 5.5 V | 5 |
| Input voltage | VI | 0 | | | V | max = VCC | 5 |
| Output voltage | VO | 0 | | | V | max = VCC | 5 |
| High-level output current | IOH | | | -12 | mA | VCC = 3 V | 5 |
| High-level output current | IOH | | | -24 | mA | VCC = 4.5 V | 5 |
| Low-level output current | IOL | | | 12 | mA | VCC = 3 V | 5 |
| Low-level output current | IOL | | | 24 | mA | VCC = 4.5 V | 5 |
| Input transition rise or fall rate | ∆t/∆v | | | 8 | ns/V | | 5 |
| Operating free-air temperature | TA | -55 | | 125 | °C | | 5 |
| High-level output voltage | VOH | 2.9 | | | V | IOH = -50µA, VCC = 3 V | 6 |
| High-level output voltage | VOH | 4.4 | | | V | IOH = -50µA, VCC = 4.5 V | 6 |
| High-level output voltage | VOH | 5.4 | | | V | IOH = -50µA, VCC = 5.5 V | 6 |
| High-level output voltage | VOH | 2.4 | | | V | IOH = -12mA, VCC = 3 V | 6 |
| High-level output voltage | VOH | 3.7 | | | V | IOH = -24mA, VCC = 4.5 V | 6 |
| High-level output voltage | VOH | 4.7 | | | V | IOH = -24mA, VCC = 5.5 V | 6 |
| Low-level output voltage | VOL | | 0.002 | 0.1 | V | IOL = 50 µA, VCC = 3 V, TA = 25°C typ | 6 |
| Low-level output voltage | VOL | | 0.001 | 0.1 | V | IOL = 50 µA, VCC = 4.5 V, TA = 25°C typ | 6 |
| Low-level output voltage | VOL | | 0.36 | 0.5 | V | IOL = 12mA, VCC = 3 V, TA = 25°C typ | 6 |
| Input current | II | -1 | | 1 | µA | A or B ports, VI = VCC or GND, VCC = 5.5 V | 6 |
| Quiescent supply current | ICC | | 2 | 40 | µA | VI = VCC or GND, IO = 0, VCC = 5.5 V | 6 |
| Propagation delay low-to-high, VCC = 3.3V ± 0.3V | tPLH | 1 | 7 | 12 | ns | A or B to Y, VCC = 3.3 V ± 0.3 V | 7 |
| Propagation delay high-to-low, VCC = 3.3V ± 0.3V | tPHL | 1 | 7 | 11.5 | ns | A or B to Y, VCC = 3.3 V ± 0.3 V | 7 |
| Propagation delay low-to-high, VCC = 5V ± 0.5V | tPLH | 1 | 5.5 | 9 | ns | A or B to Y, VCC = 5 V ± 0.5 V | 7 |
| Propagation delay high-to-low, VCC = 5V ± 0.5V | tPHL | 1 | 5 | 8.5 | ns | A or B to Y, VCC = 5 V ± 0.5 V | 7 |
| Junction-to-ambient thermal resistance (PW, TSSOP) | RθJA | | 145.7 | | °C/W | PW (TSSOP) 14-pin package | 6 |
## CAD (KiCad official)
- Symbol: `SN74AC32PWR`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `sn74ac32pwr-etched.step` / `sn74ac32pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ac32pwr.step` / `sn74ac32pwr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74ac32.pdf) (39 pp, sha256 `812fdbbf4f81846e`, retrieved 2026-10-17, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `off` (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74ac32pwr-datasheet.pdf)