component
SN74AC245N
Public Made by Adomby adom
Texas Instruments Buffers / Drivers, PDIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 8d ago |
| viewers | 8d ago |
| package.json | 8d ago |
| page.json | 8d ago |
| README.md | 8d ago |
| sn74ac245n-etched.glb | 8d ago |
| sn74ac245n-etched.step | 8d ago |
| sn74ac245n-hero.glb | 8d ago |
| sn74ac245n-hero.overlay.json | 8d ago |
| sn74ac245n.glb | 8d ago |
| sn74ac245n.kicad_mod | 8d ago |
| sn74ac245n.kicad_sym | 8d ago |
| sn74ac245n.lbr | 8d ago |
| sn74ac245n.step | 8d ago |
SN74AC245N
Texas Instruments · Buffers / Drivers · PDIP-20
SN74AC245N from Texas Instruments, in a PDIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DIR | input | Direction control input that selects A-to-B (high) or B-to-A (low) data transmission when OE is low. |
| 2 | A1 | bidirectional | A1 bus input/output, outputs data to B1 when DIR is high and receives from B1 when DIR is low. |
| 3 | A2 | bidirectional | A2 bus input/output, port paired with B2. |
| 4 | A3 | bidirectional | A3 bus input/output, port paired with B3. |
| 5 | A4 | bidirectional | A4 bus input/output, port paired with B4. |
| 6 | A5 | bidirectional | A5 bus input/output, port paired with B5. |
| 7 | A6 | bidirectional | A6 bus input/output, port paired with B6. |
| 8 | A7 | bidirectional | A7 bus input/output, port paired with B7. |
| 9 | A8 | bidirectional | A8 bus input/output, port paired with B8. |
| 10 | GND | power_in | Ground pin. |
| 11 | B8 | bidirectional | B8 bus input/output, port paired with A8. |
| 12 | B7 | bidirectional | B7 bus input/output, port paired with A7. |
| 13 | B6 | bidirectional | B6 bus input/output, port paired with A6. |
| 14 | B5 | bidirectional | B5 bus input/output, port paired with A5. |
| 15 | B4 | bidirectional | B4 bus input/output, port paired with A4. |
| 16 | B3 | bidirectional | B3 bus input/output, port paired with A3. |
| 17 | B2 | bidirectional | B2 bus input/output, port paired with A2. |
| 18 | B1 | bidirectional | B1 bus input/output, port paired with A1. |
| 19 | OE | input | Output enable input; high isolates the buses, and it should be tied to VCC through a pullup resistor to ensure high-impedance during power up or power down. |
| 20 | VCC | power_in | Power supply pin, operating range 2 V to 6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-20 |
| Category | Logic ICs |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0 or VI > VCC | 4 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VCC | 4 | |
| Continuous output current | IO | -65 | 50 | mA | VO = 0 to VCC | 4 | |
| Continuous current through VCC or GND | -200 | 200 | mA | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| ESD HBM | V(ESD) | -3000 | 3000 | V | Human body model, ANSI/ESDA/JEDEC JS-001 | 4 | |
| ESD CDM | V(ESD) | -1000 | 1000 | V | Charged-device model, JESD22-C101 | 4 | |
| Supply voltage | VCC | 2 | 6 | V | 5 | ||
| High-level input voltage | VIH | 2.1 | V | VCC = 3 V | 5 | ||
| High-level input voltage | VIH | 3.15 | V | VCC = 4.5 V | 5 | ||
| High-level input voltage | VIH | 3.85 | V | VCC = 5.5 V | 5 | ||
| Low-level input voltage | VIL | 0.9 | V | VCC = 3 V | 5 | ||
| Low-level input voltage | VIL | 1.35 | V | VCC = 4.5 V | 5 | ||
| Low-level input voltage | VIL | 1.65 | V | VCC = 5.5 V | 5 | ||
| Input voltage | VI | 0 | 6 | V | 0 to VCC | 5 | |
| Output voltage | VO | 0 | 6 | V | 0 to VCC | 5 | |
| High-level output current | IOH | -12 | mA | VCC = 3 V | 5 | ||
| High-level output current | IOH | -24 | mA | VCC = 4.5 V | 5 | ||
| Low-level output current | IOL | 12 | mA | VCC = 3 V | 5 | ||
| Low-level output current | IOL | 24 | mA | VCC = 4.5 V | 5 | ||
| Input transition rise or fall rate | Δt/Δv | 8 | ns/V | 5 | |||
| Operating free-air temperature | TA | -40 | 85 | °C | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 69 | °C/W | N (PDIP) 20 pins | 5 | ||
| High-level output voltage | VOH | 2.9 | V | IOH = −50 µA, VCC = 3 V | 6 | ||
| High-level output voltage | VOH | 4.4 | V | IOH = −50 µA, VCC = 4.5 V | 6 | ||
| High-level output voltage | VOH | 5.4 | V | IOH = −50 µA, VCC = 5.5 V | 6 | ||
| High-level output voltage | VOH | 2.46 | V | IOH = −12 mA, VCC = 3 V | 6 | ||
| High-level output voltage | VOH | 3.76 | V | IOH = −24 mA, VCC = 4.5 V | 6 | ||
| High-level output voltage | VOH | 4.76 | V | IOH = −24 mA, VCC = 5.5 V | 6 | ||
| High-level output voltage | VOH | 3.85 | V | IOH = 50 mA, VCC = 5.5 V | 6 | ||
| Low-level output voltage | VOL | 0.1 | V | IOL = 50 µA, VCC = 3 V | 6 | ||
| Low-level output voltage | VOL | 0.44 | V | IOL = 12 mA, VCC = 3 V | 6 | ||
| Low-level output voltage | VOL | 1.65 | V | IOL = 50 mA, VCC = 5.5 V | 6 | ||
| Input current A or B ports | II | -1 | 1 | µA | VI = VCC or 0, VCC = 5.5 V | 6 | |
| Input current OE or DIR | II | -1 | 1 | µA | VI = VCC or 0, VCC = 5.5 V | 6 | |
| Off-state output current | IOZ | -5 | 5 | µA | VO = VCC or GND, VI(OE) = VIL or VIH, VCC = 5.5 V | 6 | |
| Supply current | ICC | 40 | µA | VI = VCC or GND, IO = 0, VCC = 5.5 V | 6 | ||
| Input capacitance | Ci | 4.5 | pF | VI = VCC or GND, VCC = 5 V | 6 | ||
| Input/output capacitance | Cio | 15 | pF | VO = VCC or GND, VCC = 5 V | 6 | ||
| Propagation delay A or B to B or A | tPLH | 1 | 9 | ns | VCC = 3.3 V ± 0.3 V | 6 | |
| Output enable time OE to A or B | tPZH | 2 | 12.5 | ns | VCC = 3.3 V ± 0.3 V | 6 | |
| Output enable time OE to A or B | tPZL | 2 | 13.5 | ns | VCC = 3.3 V ± 0.3 V | 6 | |
| Output disable time OE to A or B | tPHZ | 1 | 12.5 | ns | VCC = 3.3 V ± 0.3 V | 6 | |
| Output disable time OE to A or B | tPLZ | 1.5 | 13 | ns | VCC = 3.3 V ± 0.3 V | 6 | |
| Propagation delay A or B to B or A | tPLH | 1 | 7 | ns | VCC = 5 V ± 0.5 V | 7 | |
| Output enable time OE to A or B | tPZH | 1 | 9 | ns | VCC = 5 V ± 0.5 V | 7 | |
| Output enable time OE to A or B | tPZL | 1 | 9.5 | ns | VCC = 5 V ± 0.5 V | 7 | |
| Output disable time OE to A or B | tPHZ | 1 | 10 | ns | VCC = 5 V ± 0.5 V | 7 | |
| Power dissipation capacitance per transceiver | Cpd | 45 | pF | CL = 50 pF, f = 1 MHz, VCC = 5 V, TA = 25°C | 7 |
CAD (KiCad official)
- Symbol:
SN74AC245N - Footprint:
Package_DIP:DIP-20_W7.62mm - 3D model: PDIP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74ac245n-etched.step/sn74ac245n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ac245n.step/sn74ac245n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (33 pp, sha256
a18293ff3ade9e58, retrieved 2026-10-22, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).