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SN74AC240QPWRQ1

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Texas Instruments Logic ICs, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74AC240QPWRQ1

Texas Instruments · Logic ICs · TSSOP-20

SN74AC240QPWRQ1 from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Output enable for buffer 1 (active low): when low the 1Y outputs pass inverted data from the 1A inputs, and when high the outputs are in the high-impedance state.
2 1A1 input Data input to buffer 1, channel 1; inputs accept voltages up to 6 V and unused inputs must be held at VCC or GND.
3 2Y4 tri_state Inverting 3-state output of buffer 2, channel 4, high-impedance when 2OE is high.
4 1A2 input Data input to buffer 1, channel 2; inputs accept voltages up to 6 V and unused inputs must be held at VCC or GND.
5 2Y3 tri_state Inverting 3-state output of buffer 2, channel 3, high-impedance when 2OE is high.
6 1A3 input Data input to buffer 1, channel 3; inputs accept voltages up to 6 V and unused inputs must be held at VCC or GND.
7 2Y2 tri_state Inverting 3-state output of buffer 2, channel 2, high-impedance when 2OE is high.
8 1A4 input Data input to buffer 1, channel 4; inputs accept voltages up to 6 V and unused inputs must be held at VCC or GND.
9 2Y1 tri_state Inverting 3-state output of buffer 2, channel 1, high-impedance when 2OE is high.
10 GND power_in Ground reference for the device.
11 2A1 input Data input to buffer 2, channel 1; inputs accept voltages up to 6 V and unused inputs must be held at VCC or GND.
12 1Y4 tri_state Inverting 3-state output of buffer 1, channel 4, high-impedance when 1OE is high.
13 2A2 input Data input to buffer 2, channel 2; inputs accept voltages up to 6 V and unused inputs must be held at VCC or GND.
14 1Y3 tri_state Inverting 3-state output of buffer 1, channel 3, high-impedance when 1OE is high.
15 2A3 input Data input to buffer 2, channel 3; inputs accept voltages up to 6 V and unused inputs must be held at VCC or GND.
16 1Y2 tri_state Inverting 3-state output of buffer 1, channel 2, high-impedance when 1OE is high.
17 2A4 input Data input to buffer 2, channel 4; inputs accept voltages up to 6 V and unused inputs must be held at VCC or GND.
18 1Y1 tri_state Inverting 3-state output of buffer 1, channel 1, high-impedance when 1OE is high.
19 2OE input Output enable for buffer 2 (active low): when low the 2Y outputs pass inverted data from the 2A inputs, and when high the outputs are in the high-impedance state.
20 VCC power_in Supply voltage, 2 V to 6 V; OE should be tied to VCC through a pullup resistor to keep outputs high-impedance during power up or down.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 2
Input voltage range VI -0.5 V upper limit printed as VCC + 0.5 V (see Note 1) 2
Output voltage range VO -0.5 V upper limit printed as VCC + 0.5 V (see Note 1) 2
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 2
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 2
Continuous output current IO -50 50 mA VO = 0 to VCC 2
Continuous current through VCC or GND -200 200 mA 2
Package thermal impedance PW package θJA 83 °C/W PW package, per JESD 51-7 2
Storage temperature range Tstg -65 150 °C 2
Supply voltage VCC 2 6 V 3
High-level input voltage VIH 2.1 V VCC = 3 V 3
High-level input voltage VIH 3.15 V VCC = 4.5 V 3
High-level input voltage VIH 3.85 V VCC = 5.5 V 3
Low-level input voltage VIL 0.9 V VCC = 3 V 3
Low-level input voltage VIL 1.35 V VCC = 4.5 V 3
Low-level input voltage VIL 1.65 V VCC = 5.5 V 3
Input voltage VI 0 V upper limit printed as VCC 3
Output voltage VO 0 V upper limit printed as VCC 3
High-level output current IOH -12 mA VCC = 3 V 3
High-level output current IOH -24 mA VCC = 4.5 V 3
Low-level output current IOL 12 mA VCC = 3 V 3
Low-level output current IOL 24 mA VCC = 4.5 V 3
Input transition rise or fall rate ∆t/∆v 8 ns/V 3
Operating free-air temperature TA -40 125 °C 3
High-level output voltage VOH 2.9 V IOH = −50 µA, VCC = 3 V; TA = −40 to 125°C 4
High-level output voltage VOH 4.4 V IOH = −50 µA, VCC = 4.5 V; TA = −40 to 125°C 4
High-level output voltage VOH 5.4 V IOH = −50 µA, VCC = 5.5 V; TA = −40 to 125°C 4
High-level output voltage VOH 2.4 V IOH = −12 mA, VCC = 3 V; TA = −40 to 125°C 4
High-level output voltage VOH 3.7 V IOH = −24 mA, VCC = 4.5 V; TA = −40 to 125°C 4
High-level output voltage VOH 4.7 V IOH = −24 mA, VCC = 5.5 V; TA = −40 to 125°C 4
High-level output voltage VOH 3.85 V IOH = −50 mA†, VCC = 5.5 V 4
Low-level output voltage VOL 0.1 V IOL = 50 µA, VCC = 3 V; TA = −40 to 125°C 4
Low-level output voltage VOL 0.5 V IOL = 12 mA, VCC = 3 V; TA = −40 to 125°C 4
Low-level output voltage VOL 1.65 V IOL = 50 mA†, VCC = 5.5 V 4
Data input current II -1 1 µA Data inputs, VI = VCC or GND, VCC = 5.5 V; TA = −40 to 125°C 4
Control input current II -1 1 µA Control inputs (OE), VI = VCC or GND, VCC = 5.5 V; TA = −40 to 125°C 4
Off-state output current IOZ -5 5 µA VO = VCC or GND, VI(OE) = VIL or VIH, VCC = 5.5 V; TA = −40 to 125°C; includes input leakage for I/O ports 4
Supply current ICC 4 80 µA VI = VCC or GND, IO = 0, VCC = 5.5 V; typ at TA = 25°C, max at TA = −40 to 125°C 4
Propagation delay tPLH (A to Y) tPLH 1 6 11 ns A to Y, VCC = 3.3 V ± 0.3 V; min/max at TA = −40 to 125°C, typ at TA = 25°C 4
Propagation delay tPHL (A to Y) tPHL 1 5.5 10.5 ns A to Y, VCC = 3.3 V ± 0.3 V; min/max at TA = −40 to 125°C, typ at TA = 25°C 4
Output enable time tPZH (OE to Y) tPZH 1 6 11.5 ns OE to Y, VCC = 3.3 V ± 0.3 V; min/max at TA = −40 to 125°C, typ at TA = 25°C 4
Output enable time tPZL (OE to Y) tPZL 1 7 13 ns OE to Y, VCC = 3.3 V ± 0.3 V; min/max at TA = −40 to 125°C, typ at TA = 25°C 4
Output disable time tPHZ (OE to Y) tPHZ 1 7 12.5 ns OE to Y, VCC = 3.3 V ± 0.3 V; min/max at TA = −40 to 125°C, typ at TA = 25°C 4
Output disable time tPLZ (OE to Y) tPLZ 1 7.5 13.5 ns OE to Y, VCC = 3.3 V ± 0.3 V; min/max at TA = −40 to 125°C, typ at TA = 25°C 4
Propagation delay tPLH (A to Y) tPLH 1 4.5 8.5 ns A to Y, VCC = 5 V ± 0.5 V; min/max at TA = −40 to 125°C, typ at TA = 25°C 5
Propagation delay tPHL (A to Y) tPHL 1 4.5 8 ns A to Y, VCC = 5 V ± 0.5 V; min/max at TA = −40 to 125°C, typ at TA = 25°C 5
Output enable time tPZH (OE to Y) tPZH 1 5 9 ns OE to Y, VCC = 5 V ± 0.5 V; min/max at TA = −40 to 125°C, typ at TA = 25°C 5
Output enable time tPZL (OE to Y) tPZL 1 5.5 10.5 ns OE to Y, VCC = 5 V ± 0.5 V; min/max at TA = −40 to 125°C, typ at TA = 25°C 5
Output disable time tPHZ (OE to Y) tPHZ 1 6.5 10.5 ns OE to Y, VCC = 5 V ± 0.5 V; min/max at TA = −40 to 125°C, typ at TA = 25°C 5
Output disable time tPLZ (OE to Y) tPLZ 1 6.5 11 ns OE to Y, VCC = 5 V ± 0.5 V; min/max at TA = −40 to 125°C, typ at TA = 25°C 5

CAD (KiCad official)

  • Symbol: SN74AC240QPWRQ1
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74ac240qpwrq1-etched.step / sn74ac240qpwrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ac240qpwrq1.step / sn74ac240qpwrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (14 pp, sha256 b3d5bdf7557b8bea, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF