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SN74AC11PWR

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Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74AC11PWR

Texas Instruments · Logic Gates · TSSOP-14

SN74AC11PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Input A of gate 1 of the triple 3-input AND (Y = A•B•C); unused inputs must be tied to VCC or GND and must not be left floating.
2 1B input Input B of gate 1 of the triple 3-input AND (Y = A•B•C); unused inputs must be tied to VCC or GND and must not be left floating.
3 2A input Input A of gate 2 of the triple 3-input AND (Y = A•B•C); unused inputs must be tied to VCC or GND and must not be left floating.
4 2B input Input B of gate 2 of the triple 3-input AND (Y = A•B•C); unused inputs must be tied to VCC or GND and must not be left floating.
5 2C input Input C of gate 2 of the triple 3-input AND (Y = A•B•C); unused inputs must be tied to VCC or GND and must not be left floating.
6 2Y output Output Y of gate 2; Y = A•B•C in positive logic.
7 GND power_in Ground reference for the device.
8 3Y output Output Y of gate 3; Y = A•B•C in positive logic.
9 3C input Input C of gate 3 per the pin name column; the table's description text for this pin reads 'Input Channel 3, Input A' (see review_required).
10 3B input Input B of gate 3 of the triple 3-input AND (Y = A•B•C); unused inputs must be tied to VCC or GND and must not be left floating.
11 3A input Input A of gate 3 per the pin name column; the table's description text for this pin reads 'Input Channel 3, Input C' (see review_required).
12 1Y output Output Y of gate 1; Y = A•B•C in positive logic.
13 1C input Input C of gate 1 of the triple 3-input AND (Y = A•B•C); unused inputs must be tied to VCC or GND and must not be left floating.
14 VCC power_in Positive supply, 2 V to 6 V operation per recommended operating conditions; each VCC terminal should have a 0.1-µF bypass capacitor placed as close to the pin as possible.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: SN74AC11PWR
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74ac11pwr-etched.step / sn74ac11pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ac11pwr.step / sn74ac11pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (38 pp, sha256 a291bc8216f06992, retrieved 2026-10-12, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF