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SN74ABTH25245DWR

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Texas Instruments Latches, SOIC-24-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icssn74abth25245dwrfactory-2.0.0extractor-text

Verified SN74ABTH25245DWR

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 24 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: SN74ABTH25245DWR · SOIC-24-300mil · 24 pins
  • ✓copper: 24 copper pads, none touching another net
  • ✓datasheet: all 24 pin names found in the 14-page datasheet
  • ✓distributor: lcsc C2878406, digikey 296-14684-2-ND, mouser 595-SN74ABTH25245DWR
  • ✓family: SOIC-24W_7.5x15.4mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-r9ry9bog/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): the datasheet dimensions give no height or body size to compare
  • ✓pads: 24 pins = 24 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 24 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ sn74abth25245dwr.kicad_sym✓ sn74abth25245dwr.kicad_mod✓ sn74abth25245dwr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray 10h ago
viewers sn74abth25245dwr: viewers · Ray 10h ago
package.json Publish 0.1.0 · Ray 10h ago
page.json Set visibility: public · Ray 10h ago
README.md Publish 0.1.0 · Ray 10h ago
sn74abth25245dwr-etched.glb Publish 0.1.0 · Ray 10h ago
sn74abth25245dwr-etched.step sn74abth25245dwr: factory component page (tier=mfr) · Ray 10h ago
sn74abth25245dwr-hero.glb sn74abth25245dwr: hero GLB from the etched model (keeps the MPN mark) · Ray 10h ago
sn74abth25245dwr-hero.overlay.json Publish 0.1.0 · Ray 10h ago
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sn74abth25245dwr.kicad_mod Publish 0.1.0 · Ray 10h ago
sn74abth25245dwr.kicad_sym Publish 0.1.0 · Ray 10h ago
sn74abth25245dwr.lbr Publish 0.1.0 · Ray 10h ago
sn74abth25245dwr.step Publish 0.1.0 · Ray 10h ago
verification.json Verified: Published by the parts factory: tier mfr, 24 pins · Ray 10h ago

SN74ABTH25245DWR

Texas Instruments · Latches · SOIC-24-300mil

SN74ABTH25245DWR from Texas Instruments, in a SOIC-24-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 bidirectional Bidirectional 3-state data pin of the A bus (channel 1); bus hold on data inputs holds an unused or floating input at a valid logic level.
2 GND power_in Ground reference; the distributed GND pin configuration minimizes high-speed switching noise.
3 A2 bidirectional Bidirectional 3-state data pin of the A bus (channel 2); bus hold on data inputs holds an unused or floating input at a valid logic level.
4 A3 bidirectional Bidirectional 3-state data pin of the A bus (channel 3); bus hold on data inputs holds an unused or floating input at a valid logic level.
5 GND power_in Ground reference; the distributed GND pin configuration minimizes high-speed switching noise.
6 A4 bidirectional Bidirectional 3-state data pin of the A bus (channel 4); bus hold on data inputs holds an unused or floating input at a valid logic level.
7 A5 bidirectional Bidirectional 3-state data pin of the A bus (channel 5); bus hold on data inputs holds an unused or floating input at a valid logic level.
8 GND power_in Ground reference; the distributed GND pin configuration minimizes high-speed switching noise.
9 A6 bidirectional Bidirectional 3-state data pin of the A bus (channel 6); bus hold on data inputs holds an unused or floating input at a valid logic level.
10 A7 bidirectional Bidirectional 3-state data pin of the A bus (channel 7); bus hold on data inputs holds an unused or floating input at a valid logic level.
11 GND power_in Ground reference; the distributed GND pin configuration minimizes high-speed switching noise.
12 A8 bidirectional Bidirectional 3-state data pin of the A bus (channel 8); bus hold on data inputs holds an unused or floating input at a valid logic level.
13 OE input Output enable, active low: when low the device is active, and when high both buses are effectively isolated.
14 B8 bidirectional Bidirectional 3-state data pin of the B bus (channel 8); bus hold on data inputs holds an unused or floating input at a valid logic level.
15 B7 bidirectional Bidirectional 3-state data pin of the B bus (channel 7); bus hold on data inputs holds an unused or floating input at a valid logic level.
16 VCC power_in Supply voltage pin; the distributed VCC pin configuration minimizes high-speed switching noise.
17 B6 bidirectional Bidirectional 3-state data pin of the B bus (channel 6); bus hold on data inputs holds an unused or floating input at a valid logic level.
18 B5 bidirectional Bidirectional 3-state data pin of the B bus (channel 5); bus hold on data inputs holds an unused or floating input at a valid logic level.
19 B4 bidirectional Bidirectional 3-state data pin of the B bus (channel 4); bus hold on data inputs holds an unused or floating input at a valid logic level.
20 B3 bidirectional Bidirectional 3-state data pin of the B bus (channel 3); bus hold on data inputs holds an unused or floating input at a valid logic level.
21 VCC power_in Supply voltage pin; the distributed VCC pin configuration minimizes high-speed switching noise.
22 B2 bidirectional Bidirectional 3-state data pin of the B bus (channel 2); bus hold on data inputs holds an unused or floating input at a valid logic level.
23 B1 bidirectional Bidirectional 3-state data pin of the B bus (channel 1); bus hold on data inputs holds an unused or floating input at a valid logic level.
24 DIR input Direction control: low selects B data to the A bus, and high selects A data to the B bus.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-24-300mil
Category Logic ICs
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5.5 V 4
High-level input voltage VIH 2 V 4
Low-level input voltage VIL 0.8 V 4
Input voltage VI 0 V 4
Input clamp current IIK -18 mA 4
High-level output current, A port IOH -80 mA A port 4
High-level output current, B port IOH -32 mA B port 4
Low-level output current, A port IOL 188 mA A port 4
Low-level output current, B port IOL 64 mA B port 4
Input transition rise or fall rate, control inputs Δt/Δv 4 ns/V Outputs enabled, control inputs 4
Input transition rise or fall rate, A or B ports Δt/Δv 10 ns/V Outputs enabled, A or B ports 4
Power-up ramp rate Δt/ΔVCC 200 µs/V 4
Operating free-air temperature TA -40 85 °C SN74ABTH25245 4
Input clamp voltage VIK -1.2 V VCC = 4.5 V, II = -18 mA 5
High-level output voltage, A port VOH 2.7 V VCC = 4.75 V, IOH = -3 mA 5
High-level output voltage, A port VOH 2.4 V VCC = 4.5 V, IOH = -80 mA 5
High-level output voltage, B port VOH 2.5 V VCC = 4.5 V, IOH = -3 mA 5
High-level output voltage, B port VOH 3 V VCC = 5 V, IOH = -3 mA 5
High-level output voltage VOH 2 V VCC = 4.5 V, IOH = -32 mA 5
Low-level output voltage, A port VOL 0.55 V VCC = 4.5 V, IOL = 94 mA 5
Low-level output voltage, A port VOL 0.7 V VCC = 4.5 V, IOL = 188 mA 5
Low-level output voltage, B port VOL 0.55 V VCC = 4.5 V, IOL = 64 mA 5
Input current, control inputs II -1 1 µA VCC = 0 to 5.5 V, VI = VCC or GND 5
Input current, A or B ports II -20 20 µA VCC = 2.1 V to 5.5 V, VI = VCC or GND 5
Bus-hold current, A or B ports II(hold) 100 µA VCC = 4.5 V, VI = 0.8 V 5
Bus-hold current, A or B ports II(hold) -100 µA VCC = 4.5 V, VI = 2 V 5
Off-state output current, power-up IOZPU -50 50 µA VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X 5
Off-state output current, power-down IOZPD -50 50 µA VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X 5
Power-off input/output current Ioff -100 100 µA VCC = 0, VI or VO ≤ 4.5 V 5
Output high leakage current ICEX 50 µA VCC = 5.5 V, VO = 5.5 V 5
Short-circuit output current, B port IO -50 -210 mA B port, VCC = 5.5 V, VO = 2.5 V 5
Supply current, outputs high ICC 500 µA VCC = 5.5 V, Outputs high 5
Supply current, outputs low ICC 20 mA VCC = 5.5 V, Outputs open, Outputs low, VI = VCC or GND 5
Supply current, outputs disabled ICC 500 µA VCC = 5.5 V, Outputs disabled, VI = VCC or GND 5
Supply current increase per input at TTL level ΔICC 1 mA VCC = 5.5 V, one input at 3.4 V, other inputs at VCC or GND 5
Propagation delay, A or B to B or A (low-to-high) tPLH 1 3.9 ns CL = 50 pF (see Figure 1) 6
Propagation delay, A or B to B or A (high-to-low) tPHL 1 4.3 ns CL = 50 pF (see Figure 1) 6
Enable time, OE to A or B (low-to-high output) tPZH 1.5 6.5 ns CL = 50 pF (see Figure 1) 6
Enable time, OE to A or B (high-to-low output) tPZL 1.4 6.8 ns CL = 50 pF (see Figure 1) 6
Disable time, OE to A or B (high-to-Z) tPHZ 2 7.2 ns CL = 50 pF (see Figure 1) 6
Disable time, OE to A or B (low-to-Z) tPLZ 2 6.4 ns CL = 50 pF (see Figure 1) 6
Supply voltage range VCC -0.5 7 V 3
Input voltage range (except I/O ports) VI -0.5 7 V 3
Voltage applied to any output in disabled or power-off state VO -0.5 5.5 V 3
Voltage applied to any output in high state VO -0.5 V 3
Input clamp current IIK -18 mA VI < 0 3
Output clamp current IOK -50 mA VO < 0 3
Current into any output in low state, A port IO 376 mA SN74ABTH25245 (A port) 3
Current into any output in low state, B port IO 128 mA SN74ABTH25245 (B port) 3
Storage temperature range Tstg -65 150 °C 3
Package thermal impedance, DW package θJA 81 °C/W DW package, per EIA/JEDEC JESD51 3

CAD (KiCad official)

  • Symbol: SN74ABTH25245DWR
  • Footprint: Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm
  • 3D model: SOIC-24-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74abth25245dwr-etched.step / sn74abth25245dwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74abth25245dwr.step / sn74abth25245dwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (14 pp, sha256 ca38e88d2213ad30, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF