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SN74ABTH245PWR
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Texas Instruments Logic ICs, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74ABTH245PWR
Texas Instruments · Logic ICs · TSSOP-20
SN74ABTH245PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DIR | input | Direction-control input: a low level selects B-data-to-A-bus transfer and a high level selects A-data-to-B-bus transfer (function table, page 2). |
| 2 | A1 | bidirectional | A-bus 3-state port that transmits to or receives from the B bus depending on DIR, and is disabled to high impedance when OE is high; data inputs have active bus hold. |
| 3 | A2 | bidirectional | A-bus 3-state port that transmits to or receives from the B bus depending on DIR, and is disabled to high impedance when OE is high; data inputs have active bus hold. |
| 4 | A3 | bidirectional | A-bus 3-state port that transmits to or receives from the B bus depending on DIR, and is disabled to high impedance when OE is high; data inputs have active bus hold. |
| 5 | A4 | bidirectional | A-bus 3-state port that transmits to or receives from the B bus depending on DIR, and is disabled to high impedance when OE is high; data inputs have active bus hold. |
| 6 | A5 | bidirectional | A-bus 3-state port that transmits to or receives from the B bus depending on DIR, and is disabled to high impedance when OE is high; data inputs have active bus hold. |
| 7 | A6 | bidirectional | A-bus 3-state port that transmits to or receives from the B bus depending on DIR, and is disabled to high impedance when OE is high; data inputs have active bus hold. |
| 8 | A7 | bidirectional | A-bus 3-state port that transmits to or receives from the B bus depending on DIR, and is disabled to high impedance when OE is high; data inputs have active bus hold. |
| 9 | A8 | bidirectional | A-bus 3-state port that transmits to or receives from the B bus depending on DIR, and is disabled to high impedance when OE is high; data inputs have active bus hold. |
| 10 | GND | power_in | Ground reference pin for the device. |
| 11 | B8 | bidirectional | B-bus 3-state port that transmits to or receives from the A bus depending on DIR, and is disabled to high impedance when OE is high; data inputs have active bus hold. |
| 12 | B7 | bidirectional | B-bus 3-state port that transmits to or receives from the A bus depending on DIR, and is disabled to high impedance when OE is high; data inputs have active bus hold. |
| 13 | B6 | bidirectional | B-bus 3-state port that transmits to or receives from the A bus depending on DIR, and is disabled to high impedance when OE is high; data inputs have active bus hold. |
| 14 | B5 | bidirectional | B-bus 3-state port that transmits to or receives from the A bus depending on DIR, and is disabled to high impedance when OE is high; data inputs have active bus hold. |
| 15 | B4 | bidirectional | B-bus 3-state port that transmits to or receives from the A bus depending on DIR, and is disabled to high impedance when OE is high; data inputs have active bus hold. |
| 16 | B3 | bidirectional | B-bus 3-state port that transmits to or receives from the A bus depending on DIR, and is disabled to high impedance when OE is high; data inputs have active bus hold. |
| 17 | B2 | bidirectional | B-bus 3-state port that transmits to or receives from the A bus depending on DIR, and is disabled to high impedance when OE is high; data inputs have active bus hold. |
| 18 | B1 | bidirectional | B-bus 3-state port that transmits to or receives from the A bus depending on DIR, and is disabled to high impedance when OE is high; data inputs have active bus hold. |
| 19 | OE | input | Output-enable input: a high level disables the device so the buses are effectively isolated; to keep the outputs high-impedance above 2.1 V, OE should be tied to VCC through a pullup resistor. |
| 20 | VCC | power_in | Supply voltage pin; recommended operating supply range is 4.5 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Logic ICs |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.5 | 5.5 | V | 3 | ||
| High-level input voltage | VIH | 2 | V | 3 | |||
| Low-level input voltage | VIL | 0.8 | V | 3 | |||
| Input voltage | VI | 0 | V | Printed maximum is VCC | 3 | ||
| High-level output current | IOH | -32 | mA | 3 | |||
| Low-level output current | IOL | 64 | mA | 3 | |||
| Input transition rise or fall rate | Δt/Δv | 5 | ns/V | 3 | |||
| Power-up ramp rate | Δt/ΔVCC | 200 | µs/V | 3 | |||
| Operating free-air temperature | TA | -40 | 85 | °C | SN74ABTH245 | 3 | |
| Supply voltage range | VCC | -0.5 | 7 | V | 3 | ||
| Input voltage range (except I/O ports) | VI | -0.5 | 7 | V | 3 | ||
| Voltage applied to any output in the high or power-off state | VO | -0.5 | 5.5 | V | 3 | ||
| Current into any output in the low state (SN74ABTH245) | IO | 128 | mA | 3 | |||
| Input clamp current | IIK | -18 | mA | VI < 0 | 3 | ||
| Output clamp current | IOK | -50 | mA | VO < 0 | 3 | ||
| Storage temperature range | Tstg | -65 | 150 | °C | 3 | ||
| Package thermal impedance (PW package) | θJA | 83 | °C/W | Calculated per JESD 51, PW package | 3 | ||
| Input clamp voltage | VIK | -1.2 | V | VCC = 4.5 V, II = -18 mA | 4 | ||
| High-level output voltage | VOH | 2.5 | V | VCC = 4.5 V, IOH = -3 mA | 4 | ||
| High-level output voltage | VOH | 3 | V | VCC = 5 V, IOH = -3 mA | 4 | ||
| High-level output voltage | VOH | 2 | V | VCC = 4.5 V, IOH = -32 mA | 4 | ||
| Low-level output voltage | VOL | 0.55 | V | VCC = 4.5 V, IOL = 64 mA | 4 | ||
| Control inputs input current | II | -1 | 1 | µA | VCC = 0 to 5.5 V, VI = VCC or GND | 4 | |
| A or B ports input current | II | -20 | 20 | µA | VCC = 2.1 V to 5.5 V, VI = VCC or GND | 4 | |
| Bus hold input current | II(hold) | 100 | µA | VCC = 4.5 V, VI = 0.8 V | 4 | ||
| Bus hold input current | II(hold) | -100 | µA | VCC = 4.5 V, VI = 2 V | 4 | ||
| Power-up 3-state output current | IOZPU | -50 | 50 | µA | VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X | 4 | |
| Power-down 3-state output current | IOZPD | -50 | 50 | µA | VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X | 4 | |
| Power-off input/output current | Ioff | -100 | 100 | µA | VCC = 0, VI or VO ≤ 4.5 V | 4 | |
| Output high leakage current | ICEX | 50 | µA | VCC = 5.5 V, VO = 5.5 V, outputs high | 4 | ||
| Short-circuit output current | IO | -180 | -50 | mA | VCC = 5.5 V, VO = 2.5 V | 4 | |
| Supply current, outputs high | ICC | 250 | µA | VCC = 5.5 V, IO = 0, VI = VCC or GND, A or B ports outputs high | 4 | ||
| Supply current, outputs low | ICC | 30 | mA | VCC = 5.5 V, IO = 0, VI = VCC or GND, outputs low | 4 | ||
| Supply current, outputs disabled | ICC | 250 | µA | VCC = 5.5 V, IO = 0, VI = VCC or GND, outputs disabled | 4 | ||
| Increase in supply current per data input, outputs enabled | ΔICC | 1.5 | mA | VCC = 5.5 V, one input at 3.4 V, other inputs at VCC or GND, outputs enabled | 4 | ||
| Increase in supply current per data input, outputs disabled | ΔICC | 1.5 | mA | VCC = 5.5 V, one input at 3.4 V, other inputs at VCC or GND, outputs disabled | 4 | ||
| Increase in supply current per control input | ΔICC | 1.5 | mA | VCC = 5.5 V, one input at 3.4 V, other inputs at VCC or GND | 4 | ||
| Propagation delay A or B to B or A (low-to-high) | tPLH | 1 | 3.6 | ns | VCC = 5 V range, CL = 50 pF (Figure 1) | 5 | |
| Propagation delay A or B to B or A (high-to-low) | tPHL | 1 | 3.9 | ns | VCC = 5 V range, CL = 50 pF (Figure 1) | 5 | |
| Enable time OE to A or B (high) | tPZH | 2 | 5.6 | ns | VCC = 5 V range, CL = 50 pF (Figure 1) | 5 | |
| Enable time OE to A or B (low) | tPZL | 1.9 | 6.2 | ns | VCC = 5 V range, CL = 50 pF (Figure 1) | 5 | |
| Disable time OE to A or B (high) | tPHZ | 2.2 | 5.9 | ns | VCC = 5 V range, CL = 50 pF (Figure 1) | 5 | |
| Disable time OE to A or B (low) | tPLZ | 1.5 | 4.5 | ns | VCC = 5 V range, CL = 50 pF (Figure 1) | 5 | |
| Output-to-output skew | tsk(o) | 0.5 | ns | CL = 50 pF (Figure 1) | 5 |
CAD (KiCad official)
- Symbol:
SN74ABTH245PWR - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74abth245pwr-etched.step/sn74abth245pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74abth245pwr.step/sn74abth245pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (24 pp, sha256
baa0ae338c15d325, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).