component

SN74ABT574APWR

Public Made by Adom

by adom

Texas Instruments Logic ICs, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icssn74abt574apwrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 13d ago
viewers sn74abt574apwr: viewers · Ray 13d ago
package.json Publish 0.1.0 · Ray 13d ago
page.json Set visibility: public · Ray 13d ago
README.md Publish 0.1.0 · Ray 13d ago
sn74abt574apwr-etched.glb Publish 0.1.0 · Ray 13d ago
sn74abt574apwr-etched.step sn74abt574apwr: factory component page (tier=mfr) · Ray 13d ago
sn74abt574apwr-hero.glb sn74abt574apwr: hero GLB from the etched model (keeps the MPN mark) · Ray 13d ago
sn74abt574apwr-hero.overlay.json Publish 0.1.0 · Ray 13d ago
sn74abt574apwr.glb Publish 0.1.0 · Ray 13d ago
sn74abt574apwr.kicad_mod Publish 0.1.0 · Ray 13d ago
sn74abt574apwr.kicad_sym Publish 0.1.0 · Ray 13d ago
sn74abt574apwr.lbr Publish 0.1.0 · Ray 13d ago
sn74abt574apwr.step Publish 0.1.0 · Ray 13d ago

SN74ABT574APWR

Texas Instruments · Logic ICs · TSSOP-20

SN74ABT574APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Buffered active-low output-enable input; it places the eight outputs in the high-impedance state when high and should be tied to VCC through a pullup resistor to keep the outputs high-Z during power-up and power-down.
2 1D input Data input for flip-flop 1, loaded into Q on the positive CLK transition; unused inputs must be held at VCC or GND.
3 2D input Data input for flip-flop 2, loaded into Q on the positive CLK transition; unused inputs must be held at VCC or GND.
4 3D input Data input for flip-flop 3, loaded into Q on the positive CLK transition; unused inputs must be held at VCC or GND.
5 4D input Data input for flip-flop 4, loaded into Q on the positive CLK transition; unused inputs must be held at VCC or GND.
6 5D input Data input for flip-flop 5, loaded into Q on the positive CLK transition; unused inputs must be held at VCC or GND.
7 6D input Data input for flip-flop 6, loaded into Q on the positive CLK transition; unused inputs must be held at VCC or GND.
8 7D input Data input for flip-flop 7, loaded into Q on the positive CLK transition; unused inputs must be held at VCC or GND.
9 8D input Data input for flip-flop 8, loaded into Q on the positive CLK transition; unused inputs must be held at VCC or GND.
10 GND power_in Ground reference for the device.
11 CLK input Clock input; the Q outputs take the logic levels present on the D inputs on the positive clock transition, with fclock up to 150 MHz and minimum pulse width of 3.3 ns.
12 8Q tri_state Flip-flop 8 3-state output, rated for high drive (−32 mA IOH, 64 mA IOL) and disabled to high impedance by OE high.
13 7Q tri_state Flip-flop 7 3-state output, rated for high drive (−32 mA IOH, 64 mA IOL) and disabled to high impedance by OE high.
14 6Q tri_state Flip-flop 6 3-state output, rated for high drive (−32 mA IOH, 64 mA IOL) and disabled to high impedance by OE high.
15 5Q tri_state Flip-flop 5 3-state output, rated for high drive (−32 mA IOH, 64 mA IOL) and disabled to high impedance by OE high.
16 4Q tri_state Flip-flop 4 3-state output, rated for high drive (−32 mA IOH, 64 mA IOL) and disabled to high impedance by OE high.
17 3Q tri_state Flip-flop 3 3-state output, rated for high drive (−32 mA IOH, 64 mA IOL) and disabled to high impedance by OE high.
18 2Q tri_state Flip-flop 2 3-state output, rated for high drive (−32 mA IOH, 64 mA IOL) and disabled to high impedance by OE high.
19 1Q tri_state Flip-flop 1 3-state output, rated for high drive (−32 mA IOH, 64 mA IOL) and disabled to high impedance by OE high.
20 VCC power_in Supply voltage, 4.5 V to 5.5 V recommended operating range.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5.5 V 3
High-level input voltage VIH 2 V 3
Low-level input voltage VIL 0.8 V 3
Input voltage VI 0 V Printed upper limit is VCC 3
High-level output current IOH -32 mA 3
Low-level output current IOL 64 mA 3
Input transition rise or fall rate Δt/Δv 5 ns/V Outputs enabled 3
Operating free-air temperature TA -40 85 °C 3
Supply voltage range VCC -0.5 7 V 3
Input voltage range VI -0.5 7 V 3
Voltage range applied to any output in the high or power-off state VO -0.5 5.5 V 3
Current into any output in the low state IO 128 mA SN74ABT574A 3
Input clamp current IIK -18 mA VI < 0 3
Output clamp current IOK -50 mA VO < 0 3
Storage temperature range Tstg -65 150 °C 3
Input clamp voltage VIK -1.2 V VCC = 4.5 V, II = −18 mA 4
High-level output voltage VOH 2.5 V VCC = 4.5 V, IOH = −3 mA 4
High-level output voltage VOH 3 V VCC = 5 V, IOH = −3 mA 4
High-level output voltage VOH 2 V VCC = 4.5 V, IOH = −24 mA 4
Low-level output voltage VOL 0.55 V VCC = 4.5 V, IOL = 48 mA 4
Input current II -1 1 μA VCC = 5.5 V, VI = VCC or GND 4
Off-state output current, high-level voltage applied IOZH 10 μA VCC = 5.5 V, VO = 2.7 V 4
Off-state output current, low-level voltage applied IOZL -10 μA VCC = 5.5 V, VO = 0.5 V 4
Partial power down current Ioff -100 100 μA VCC = 0, VI or VO ≤ 4.5 V 4
Output high leakage current ICEX 50 μA VCC = 5.5 V, VO = 5.5 V, outputs high 4
Short-circuit output current IO -50 -100 -180 mA VCC = 5.5 V, VO = 2.5 V 4
Supply current, outputs high ICC 1 250 μA VCC = 5.5 V, IO = 0, VI = VCC or GND, outputs high 4
Supply current, outputs low ICC 24 30 mA VCC = 5.5 V, IO = 0, VI = VCC or GND, outputs low 4
Supply current, outputs disabled ICC 0.5 250 μA VCC = 5.5 V, IO = 0, VI = VCC or GND, outputs disabled 4
Increase in supply current per input at TTL level ΔICC 1.5 mA VCC = 5.5 V, one input at 3.4 V, other inputs at VCC or GND 4
Clock frequency fclock 150 MHz 5
Pulse duration, CLK high or low tw 3.3 ns CLK high or low 5
Setup time, data before CLK↑ tsu 1 ns CLK high 5
Setup time, data before CLK↑ tsu 1.5 ns CLK low 5
Hold time, data after CLK↑ th 1.8 ns High or low 5
Maximum clock frequency fmax 150 MHz CL = 50 pF 5
Propagation delay CLK to Q (low-to-high) tPLH 2.2 3.9 6.8 ns CL = 50 pF; typ at VCC = 5 V, TA = 25°C 5
Propagation delay CLK to Q (high-to-low) tPHL 3 4.8 7.1 ns CL = 50 pF; typ at VCC = 5 V, TA = 25°C 5
Enable time OE to Q (high) tPZH 1 3.3 5.1 ns CL = 50 pF; typ at VCC = 5 V, TA = 25°C 5
Enable time OE to Q (low) tPZL 2.1 4.7 6.7 ns CL = 50 pF; typ at VCC = 5 V, TA = 25°C 5
Disable time OE to Q (high) tPHZ 2.4 4.9 7 ns CL = 50 pF; typ at VCC = 5 V, TA = 25°C 5
Disable time OE to Q (low) tPLZ 2 4 6.5 ns CL = 50 pF; typ at VCC = 5 V, TA = 25°C 5
Package thermal impedance, PW package θJA 83 °C/W JESD 51-7 (Note 2) 3

CAD (KiCad official)

  • Symbol: SN74ABT574APWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74abt574apwr-etched.step / sn74abt574apwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74abt574apwr.step / sn74abt574apwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 7d8bbb1be5d32de3, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF