# SN74ABT541BIPWREP

**Texas Instruments** · Logic ICs · TSSOP-20

SN74ABT541BIPWREP from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE1 | input | Active-low output enable; when OE1 or OE2 is high, all eight outputs are placed in the high-impedance state. |
| 2 | A1 | input | Data input channel 1; VIH must be at least 2 V and VIL at most 0.8 V, and unused inputs must be held at VCC or GND. |
| 3 | A2 | input | Data input channel 2; VIH must be at least 2 V and VIL at most 0.8 V, and unused inputs must be held at VCC or GND. |
| 4 | A3 | input | Data input channel 3; VIH must be at least 2 V and VIL at most 0.8 V, and unused inputs must be held at VCC or GND. |
| 5 | A4 | input | Data input channel 4; VIH must be at least 2 V and VIL at most 0.8 V, and unused inputs must be held at VCC or GND. |
| 6 | A5 | input | Data input channel 5; VIH must be at least 2 V and VIL at most 0.8 V, and unused inputs must be held at VCC or GND. |
| 7 | A6 | input | Data input channel 6; VIH must be at least 2 V and VIL at most 0.8 V, and unused inputs must be held at VCC or GND. |
| 8 | A7 | input | Data input channel 7; VIH must be at least 2 V and VIL at most 0.8 V, and unused inputs must be held at VCC or GND. |
| 9 | A8 | input | Data input channel 8; VIH must be at least 2 V and VIL at most 0.8 V, and unused inputs must be held at VCC or GND. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | Y8 | tri_state | 3-state buffer output channel 8; rated for −32 mA IOH and 64 mA IOL, and high-impedance when OE1 or OE2 is high. |
| 12 | Y7 | tri_state | 3-state buffer output channel 7; rated for −32 mA IOH and 64 mA IOL, and high-impedance when OE1 or OE2 is high. |
| 13 | Y6 | tri_state | 3-state buffer output channel 6; rated for −32 mA IOH and 64 mA IOL, and high-impedance when OE1 or OE2 is high. |
| 14 | Y5 | tri_state | 3-state buffer output channel 5; rated for −32 mA IOH and 64 mA IOL, and high-impedance when OE1 or OE2 is high. |
| 15 | Y4 | tri_state | 3-state buffer output channel 4; rated for −32 mA IOH and 64 mA IOL, and high-impedance when OE1 or OE2 is high. |
| 16 | Y3 | tri_state | 3-state buffer output channel 3; rated for −32 mA IOH and 64 mA IOL, and high-impedance when OE1 or OE2 is high. |
| 17 | Y2 | tri_state | 3-state buffer output channel 2; rated for −32 mA IOH and 64 mA IOL, and high-impedance when OE1 or OE2 is high. |
| 18 | Y1 | tri_state | 3-state buffer output channel 1; rated for −32 mA IOH and 64 mA IOL, and high-impedance when OE1 or OE2 is high. |
| 19 | OE2 | input | Active-low output enable; when OE2 or OE1 is high, all eight outputs are placed in the high-impedance state. |
| 20 | VCC | power_in | Supply voltage, recommended 4.5 V to 5.5 V; the device is high-impedance during power up/down when VCC is between 0 and 2.1 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Logic ICs |
| Pins | 20 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.5 |  | 5.5 | V |  | 2 |
| High-level input voltage | VIH | 2 |  |  | V |  | 2 |
| Low-level input voltage | VIL |  |  | 0.8 | V |  | 2 |
| High-level output current | IOH |  |  | -32 | mA |  | 2 |
| Low-level output current | IOL |  |  | 64 | mA |  | 2 |
| Operating free-air temperature | TA | -40 |  | 85 | °C |  | 2 |
| Supply voltage range | VCC | -0.5 |  | 7 | V |  | 2 |
| Input voltage range | VI | -0.5 |  | 7 | V | see Note 1 | 2 |
| Voltage applied to any output in the high or power-off state | VO | -0.5 |  | 5.5 | V |  | 2 |
| Current into any output in the low state | IO |  |  | 128 | mA |  | 2 |
| Input clamp current | IIK | -18 |  |  | mA | VI < 0 | 2 |
| Output clamp current | IOK | -50 |  |  | mA | VO < 0 | 2 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 2 |
| Package thermal impedance | θJA |  |  | 128 | °C/W | per JESD 51, see Note 2 | 2 |
| Input clamp voltage | VIK |  |  | -1.2 | V | VCC = 4.5 V, II = −18 mA | 3 |
| High-level output voltage | VOH | 2.5 |  |  | V | VCC = 4.5 V, IOH = −3 mA | 3 |
| High-level output voltage | VOH | 3 |  |  | V | VCC = 5 V, IOH = −3 mA | 3 |
| High-level output voltage | VOH | 2 |  |  | V | VCC = 4.5 V, IOH = −32 mA | 3 |
| Low-level output voltage | VOL |  |  | 0.55 | V | VCC = 4.5 V, IOL = 64 mA | 3 |
| Input current | II | -1 |  | 1 | µA | VCC = 5.5 V, VI = VCC or GND | 3 |
| Off-state output current, power-up | IOZPU | -50 |  | 50 | µA | VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X | 3 |
| Off-state output current, power-down | IOZPD | -50 |  | 50 | µA | VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X | 3 |
| High-level off-state output current | IOZH |  |  | 10 | µA | VCC = 5.5 V, VO = 2.7 V | 3 |
| Low-level off-state output current | IOZL | -10 |  |  | µA | VCC = 5.5 V, VO = 0.5 V | 3 |
| Power-off input/output current | Ioff | -100 |  | 100 | µA | VCC = 0, VI or VO ≤ 4.5 V | 3 |
| High-level output current (ICEX) | ICEX |  |  | 50 | µA | VCC = 5.5 V, VO = 5.5 V, outputs high | 3 |
| Short-circuit output current | IO | -50 |  | -180 | mA | VCC = 5.5 V, VO = 2.5 V | 3 |
| Supply current, outputs high | ICC |  | 5 | 250 | µA | VCC = 5.5 V, IO = 0, VI = VCC or GND, outputs high | 3 |
| Supply current, outputs low | ICC |  | 22 | 30 | mA | VCC = 5.5 V, IO = 0, VI = VCC or GND, outputs low | 3 |
| Supply current, outputs disabled | ICC |  | 1 | 250 | µA | VCC = 5.5 V, IO = 0, VI = VCC or GND, outputs disabled | 3 |
| Increase in supply current per input, outputs enabled | ΔICC |  |  | 1.5 | mA | VCC = 5.5 V, one input at 3.4 V, outputs enabled | 3 |
| Increase in supply current per input, outputs disabled | ΔICC |  |  | 50 | µA | VCC = 5.5 V, one input at 3.4 V, other inputs at VCC or GND, outputs disabled | 3 |
| Increase in supply current per input, control inputs | ΔICC |  |  | 1.5 | mA | VCC = 5.5 V, one input at 3.4 V, other inputs at VCC or GND | 3 |
| Propagation delay low-to-high (A to Y) | tPLH | 1 |  | 3.6 | ns | CL = 50 pF, A to Y | 3 |
| Propagation delay high-to-low (A to Y) | tPHL | 1 |  | 3.9 | ns | CL = 50 pF, A to Y | 3 |
| Output enable time to high (OE to Y) | tPZH | 2 |  | 4 | ns | CL = 50 pF, OE to Y | 3 |
| Output enable time to low (OE to Y) | tPZL | 1.9 |  | 5.9 | ns | CL = 50 pF, OE to Y | 3 |
| Output disable time from high (OE to Y) | tPHZ | 2.2 |  | 5.8 | ns | CL = 50 pF, OE to Y | 3 |
| Output disable time from low (OE to Y) | tPLZ | 1.5 |  | 4.4 | ns | CL = 50 pF, OE to Y | 3 |
| Output-to-output skew | tsk(o) |  |  | 0.5 | ns | CL = 50 pF; between any two outputs of the same package switching in the same direction | 3 |

## CAD (KiCad official)

- Symbol: `SN74ABT541BIPWREP`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `sn74abt541bipwrep-etched.step` / `sn74abt541bipwrep-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74abt541bipwrep.step` / `sn74abt541bipwrep.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74abt541b-ep) (12 pp, sha256 `d88cc9656a387177`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74abt541bipwrep-datasheet.pdf)