# SN74ABT5403DWR

**Texas Instruments** · Inverters · SOIC-28-300mil

SN74ABT5403DWR from Texas Instruments, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y1 | tri_state | Inverted 3-state output channel 1 that sources or sinks up to 12 mA through an internal 25-Ω series resistor. |
| 2 | Y2 | tri_state | Inverted 3-state output channel 2 that sources or sinks up to 12 mA through an internal 25-Ω series resistor. |
| 3 | Y3 | tri_state | Inverted 3-state output channel 3 that sources or sinks up to 12 mA through an internal 25-Ω series resistor. |
| 4 | Y4 | tri_state | Inverted 3-state output channel 4 that sources or sinks up to 12 mA through an internal 25-Ω series resistor. |
| 5 | Y5 | tri_state | Inverted 3-state output channel 5 that sources or sinks up to 12 mA through an internal 25-Ω series resistor. |
| 6 | Y6 | tri_state | Inverted 3-state output channel 6 that sources or sinks up to 12 mA through an internal 25-Ω series resistor. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | Y7 | tri_state | Inverted 3-state output channel 7 that sources or sinks up to 12 mA through an internal 25-Ω series resistor. |
| 9 | Y8 | tri_state | Inverted 3-state output channel 8 that sources or sinks up to 12 mA through an internal 25-Ω series resistor. |
| 10 | Y9 | tri_state | Inverted 3-state output channel 9 that sources or sinks up to 12 mA through an internal 25-Ω series resistor. |
| 11 | Y10 | tri_state | Inverted 3-state output channel 10 that sources or sinks up to 12 mA through an internal 25-Ω series resistor. |
| 12 | Y11 | tri_state | Inverted 3-state output channel 11 that sources or sinks up to 12 mA through an internal 25-Ω series resistor. |
| 13 | Y12 | tri_state | Inverted 3-state output channel 12 that sources or sinks up to 12 mA through an internal 25-Ω series resistor. |
| 14 | OE1 | input | Active-low output enable; when OE1 or OE2 is high, all 12 outputs enter the high-impedance state, and it should be pulled up to VCC through a resistor during power up or down. |
| 15 | OE2 | input | Active-low output enable; when OE1 or OE2 is high, all 12 outputs enter the high-impedance state, and it should be pulled up to VCC through a resistor during power up or down. |
| 16 | D12 | input | Data input for channel 12; the output is the inverse of this input when the outputs are enabled. |
| 17 | D11 | input | Data input for channel 11; the output is the inverse of this input when the outputs are enabled. |
| 18 | D10 | input | Data input for channel 10; the output is the inverse of this input when the outputs are enabled. |
| 19 | D9 | input | Data input for channel 9; the output is the inverse of this input when the outputs are enabled. |
| 20 | D8 | input | Data input for channel 8; the output is the inverse of this input when the outputs are enabled. |
| 21 | VCC | power_in | Supply voltage, specified from 4.5 V to 5.5 V in the recommended operating conditions. |
| 22 | D7 | input | Data input for channel 7; the output is the inverse of this input when the outputs are enabled. |
| 23 | D6 | input | Data input for channel 6; the output is the inverse of this input when the outputs are enabled. |
| 24 | D5 | input | Data input for channel 5; the output is the inverse of this input when the outputs are enabled. |
| 25 | D4 | input | Data input for channel 4; the output is the inverse of this input when the outputs are enabled. |
| 26 | D3 | input | Data input for channel 3; the output is the inverse of this input when the outputs are enabled. |
| 27 | D2 | input | Data input for channel 2; the output is the inverse of this input when the outputs are enabled. |
| 28 | D1 | input | Data input for channel 1; the output is the inverse of this input when the outputs are enabled. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-28-300mil |
| Category | Logic ICs |
| Pins | 28 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.5 |  | 5.5 | V |  | 3 |
| High-level input voltage | VIH | 2 |  |  | V |  | 3 |
| Low-level input voltage | VIL |  |  | 0.8 | V |  | 3 |
| Input voltage | VI | 0 |  |  | V |  | 3 |
| High-level output current | IOH | -12 |  |  | mA |  | 3 |
| Low-level output current | IOL |  |  | 12 | mA |  | 3 |
| Input transition rise or fall rate | Δt/Δv |  |  | 10 | ns/V | Outputs enabled | 3 |
| Operating free-air temperature | TA | -40 |  | 85 | °C |  | 3 |
| Supply voltage range | VCC | -0.5 |  | 7 | V |  | 2 |
| Input voltage range | VI | -0.5 |  | 7 | V |  | 2 |
| Voltage applied to any output in the high or power-off state | VO | -0.5 |  | 5.5 | V |  | 2 |
| Current into any output in the low state | IO |  |  | 30 | mA |  | 2 |
| Input clamp current | IIK | -18 |  |  | mA | VI < 0 | 2 |
| Output clamp current | IOK | -50 |  |  | mA | VO < 0 | 2 |
| Package thermal impedance DW package | θJA |  | 78 |  | °C/W | DW package, see Note 2 | 2 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 2 |
| Input clamp voltage | VIK |  |  | -1.2 | V | VCC = 4.5 V, II = -18 mA | 3 |
| High-level output voltage | VOH | 3.35 | 3.7 |  | V | VCC = 4.5 V, IOH = -1 mA | 3 |
| High-level output voltage | VOH | 3.85 | 4.2 |  | V | VCC = 5 V, IOH = -1 mA | 3 |
| High-level output voltage | VOH | 3.1 |  |  | V | VCC = 4.5 V, IOH = -3 mA | 3 |
| High-level output voltage | VOH | 2.6 |  |  | V | VCC = 4.5 V, IOH = -12 mA | 3 |
| Low-level output voltage | VOL |  |  | 0.65 | V | VCC = 4.5 V, IOL = 8 mA | 3 |
| Low-level output voltage | VOL |  |  | 0.8 | V | VCC = 4.5 V, IOL = 12 mA | 3 |
| Hysteresis | Vhys |  | 100 |  | mV |  | 3 |
| Input current | II | -1 |  | 1 | µA | VCC = 5.5 V, VI = VCC or GND | 3 |
| Off-state output current, high-level voltage applied | IOZH |  |  | 50 | µA | VCC = 5.5 V, VO = 2.7 V | 3 |
| Off-state output current, low-level voltage applied | IOZL | -50 |  |  | µA | VCC = 5.5 V, VO = 0.5 V | 3 |
| Power-off output current | Ioff | -100 |  | 100 | µA | VCC = 0, VI or VO ≤ 4.5 V | 3 |
| Output high leakage current | ICEX |  |  | 50 | µA | VCC = 5.5 V, VO = 5.5 V, outputs high | 3 |
| Output current | IO | -100 | -45 | -25 | mA | VCC = 5.5 V, VO = 2.5 V | 3 |
| Short-circuit output current | IOS | -200 |  | -50 | mA | VCC = 5.5 V, VO = 0 | 3 |
| Supply current, outputs high | ICC |  | 5 | 50 | µA | VCC = 5.5 V, IO = 0, VI = VCC or GND, outputs high | 3 |
| Supply current, outputs low | ICC |  | 36 | 45 | mA | VCC = 5.5 V, IO = 0, VI = VCC or GND, outputs low | 3 |
| Supply current, outputs disabled | ICC |  | 1 | 50 | µA | VCC = 5.5 V, IO = 0, VI = VCC or GND, outputs disabled | 3 |
| Increase in supply current, data inputs, outputs enabled | ΔICC |  |  | 1.5 | mA | VCC = 5.5 V, one data input at 3.4 V, other inputs at VCC or GND, outputs enabled | 3 |
| Increase in supply current, data inputs, outputs disabled | ΔICC |  |  | 0.05 | mA | VCC = 5.5 V, one data input at 3.4 V, other inputs at VCC or GND, outputs disabled | 3 |
| Increase in supply current, control inputs | ΔICC |  |  | 1.5 | mA | VCC = 5.5 V, one control input at 3.4 V, other inputs at VCC or GND | 3 |
| Input capacitance | Ci |  | 3 |  | pF | VI = 2.5 V or 0.5 V | 3 |
| Output capacitance | Co |  | 8 |  | pF | VO = 2.5 V or 0.5 V | 3 |
| Propagation delay time, low-to-high-level output | tPLH | 2 | 4.5 | 6.9 | ns | D to Y, CL = 50 pF, see Figure 1 | 4 |
| Propagation delay time, high-to-low-level output | tPHL | 1.5 | 4.4 | 5.7 | ns | D to Y, CL = 50 pF, see Figure 1 | 4 |
| Output enable time to high level | tPZH | 2.5 | 5.7 | 8.5 | ns | OE to Y, CL = 50 pF, see Figure 1 | 4 |
| Output enable time to low level | tPZL | 2 | 4.4 | 6.8 | ns | OE to Y, CL = 50 pF, see Figure 1 | 4 |
| Output disable time from high level | tPHZ | 1.5 | 3.6 | 5.2 | ns | OE to Y, CL = 50 pF, see Figure 1 | 4 |
| Output disable time from low level | tPLZ | 1.5 | 4.2 | 6.9 | ns | OE to Y, CL = 50 pF, see Figure 1 | 4 |

## CAD (KiCad official)

- Symbol: `SN74ABT5403DWR`
- Footprint: `Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm`
- 3D model: SOIC-28-300mil (KiCad packages3D, STEP)
- 3D model files: `sn74abt5403dwr-etched.step` / `sn74abt5403dwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74abt5403dwr.step` / `sn74abt5403dwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74abt5403dwr.pdf) (9 pp, sha256 `0ad76cd7bab791ce`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74abt5403dwr-datasheet.pdf)