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SN74ABT5402ADWR

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Texas Instruments Buffer/Driver/Transceiver, SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icssn74abt5402adwrfactory-2.0.0extractor-text

Verified SN74ABT5402ADWR

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 28 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: SN74ABT5402ADWR · SOIC-28-300mil · 28 pins
  • ✓copper: 28 copper pads, none touching another net
  • ✓datasheet: all 28 pin names found in the 13-page datasheet
  • ✓distributor: lcsc C2868753, digikey 296-4020-2-ND, mouser 595-SN74ABT5402ADWR
  • ✓family: SOIC-28W_7.5x17.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-l9de3f22/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): the datasheet dimensions give no height or body size to compare
  • ✓pads: 28 pins = 28 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 28 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ sn74abt5402adwr.kicad_sym✓ sn74abt5402adwr.kicad_mod✓ sn74abt5402adwr.step
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Ray Publish 0.1.0 ca2fb9d 14h ago

SN74ABT5402ADWR

Texas Instruments · Buffer/Driver/Transceiver · SOIC-28-300mil

SN74ABT5402ADWR from Texas Instruments, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Y1 tri_state Buffered 3-state output of channel 1, designed to source or sink up to 12 mA with an internal 25-Ω series resistor.
2 Y2 tri_state Buffered 3-state output of channel 2, designed to source or sink up to 12 mA with an internal 25-Ω series resistor.
3 Y3 tri_state Buffered 3-state output of channel 3, designed to source or sink up to 12 mA with an internal 25-Ω series resistor.
4 Y4 tri_state Buffered 3-state output of channel 4, designed to source or sink up to 12 mA with an internal 25-Ω series resistor.
5 Y5 tri_state Buffered 3-state output of channel 5, designed to source or sink up to 12 mA with an internal 25-Ω series resistor.
6 Y6 tri_state Buffered 3-state output of channel 6, designed to source or sink up to 12 mA with an internal 25-Ω series resistor.
7 GND power_in Ground reference for the device.
8 Y7 tri_state Buffered 3-state output of channel 7, designed to source or sink up to 12 mA with an internal 25-Ω series resistor.
9 Y8 tri_state Buffered 3-state output of channel 8, designed to source or sink up to 12 mA with an internal 25-Ω series resistor.
10 Y9 tri_state Buffered 3-state output of channel 9, designed to source or sink up to 12 mA with an internal 25-Ω series resistor.
11 Y10 tri_state Buffered 3-state output of channel 10, designed to source or sink up to 12 mA with an internal 25-Ω series resistor.
12 Y11 tri_state Buffered 3-state output of channel 11, designed to source or sink up to 12 mA with an internal 25-Ω series resistor.
13 Y12 tri_state Buffered 3-state output of channel 12, designed to source or sink up to 12 mA with an internal 25-Ω series resistor.
14 OE1 input Active-low output enable; when OE1 or OE2 is high, all 12 outputs are placed in the high-impedance state, and OE should be pulled up to VCC through a resistor to ensure high impedance during power up/down.
15 OE2 input Active-low output enable; when OE2 or OE1 is high, all 12 outputs are placed in the high-impedance state, and OE should be pulled up to VCC through a resistor to ensure high impedance during power up/down.
16 D12 input Data input for channel 12, with input voltage range 0 to VCC; unused inputs must be held high or low.
17 D11 input Data input for channel 11, with input voltage range 0 to VCC; unused inputs must be held high or low.
18 D10 input Data input for channel 10, with input voltage range 0 to VCC; unused inputs must be held high or low.
19 D9 input Data input for channel 9, with input voltage range 0 to VCC; unused inputs must be held high or low.
20 D8 input Data input for channel 8, with input voltage range 0 to VCC; unused inputs must be held high or low.
21 VCC power_in Supply voltage, recommended 4.5 V to 5.5 V.
22 D7 input Data input for channel 7, with input voltage range 0 to VCC; unused inputs must be held high or low.
23 D6 input Data input for channel 6, with input voltage range 0 to VCC; unused inputs must be held high or low.
24 D5 input Data input for channel 5, with input voltage range 0 to VCC; unused inputs must be held high or low.
25 D4 input Data input for channel 4, with input voltage range 0 to VCC; unused inputs must be held high or low.
26 D3 input Data input for channel 3, with input voltage range 0 to VCC; unused inputs must be held high or low.
27 D2 input Data input for channel 2, with input voltage range 0 to VCC; unused inputs must be held high or low.
28 D1 input Data input for channel 1, with input voltage range 0 to VCC; unused inputs must be held high or low.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-28-300mil
Category Logic ICs
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5.5 V 3
High-level input voltage VIH 2 V 3
Low-level input voltage VIL 0.8 V 3
Input voltage VI 0 V 3
High-level output current IOH -12 mA 3
Low-level output current IOL 12 mA 3
Input transition rise or fall rate Δt/Δv 10 ns/V Outputs enabled 3
Operating free-air temperature TA -40 85 °C 3
Supply voltage range VCC -0.5 7 V 2
Input voltage range VI -0.5 7 V See Note 1 2
Voltage range applied to any output in the high or power-off state VO -0.5 5.5 V High or power-off state 2
Current into any output in the low state IO 30 mA Low state 2
Input clamp current IIK -18 mA VI < 0 2
Output clamp current IOK -50 mA VO < 0 2
Package thermal impedance, DW package θJA 78 °C/W DW package, see Note 2 2
Storage temperature range Tstg -65 150 °C 2
Input clamp voltage VIK -1.2 V VCC = 4.5 V, II = -18 mA 3
High-level output voltage VOH 3.35 V VCC = 4.5 V, IOH = -1 mA 3
High-level output voltage VOH 3.85 V VCC = 5 V, IOH = -1 mA 3
High-level output voltage VOH 2.6 V VCC = 4.5 V, IOH = -12 mA 3
Low-level output voltage VOL 0.65 V VCC = 4.5 V, IOL = 8 mA 3
Input current II -1 1 µA VCC = 5.5 V, VI = VCC or GND 3
Off-state output current, high-level voltage applied IOZH 10 µA VCC = 5.5 V, VO = 2.7 V 3
Off-state output current, low-level voltage applied IOZL -10 µA VCC = 5.5 V, VO = 0.5 V 3
Input/output power-off leakage current Ioff -100 100 µA VCC = 0, VI or VO ≤ 4.5 V 3
Output high leakage current ICEX 50 µA VCC = 5.5 V, VO = 5.5 V, outputs high 3
Output current IO -25 -45 -100 mA VCC = 5.5 V, VO = 2.5 V 3
Short-circuit output current IOS -50 -200 -200 mA VCC = 5.5 V, VO = 0 3
Supply current, outputs high ICC 5 50 µA VCC = 5.5 V, IO = 0, VI = VCC or GND, outputs high 3
Supply current, outputs low ICC 39 48 mA VCC = 5.5 V, IO = 0, VI = VCC or GND, outputs low 3
Supply current, outputs disabled ICC 1 50 µA VCC = 5.5 V, IO = 0, VI = VCC or GND, outputs disabled 3
Increase in supply current per data input, outputs enabled ΔICC 1.5 mA VCC = 5.5 V, one data input at 3.4 V, other inputs at VCC or GND, outputs enabled 3
Increase in supply current per data input, outputs disabled ΔICC 0.05 mA VCC = 5.5 V, one data input at 3.4 V, other inputs at VCC or GND, outputs disabled 3
Increase in supply current per control input ΔICC 1.5 mA VCC = 5.5 V, one control input at 3.4 V, other inputs at VCC or GND 3
Propagation delay, D to Y, low-to-high tPLH 2 6.2 ns CL = 50 pF 4
Propagation delay, D to Y, high-to-low tPHL 1.5 5.6 ns CL = 50 pF 4
Enable time, OE to Y, high-level output tPZH 2.5 8.7 ns CL = 50 pF 4
Enable time, OE to Y, low-level output tPZL 2 7.5 ns CL = 50 pF 4
Disable time, OE to Y, high-level output tPHZ 1.5 5.2 ns CL = 50 pF 4
Disable time, OE to Y, low-level output tPLZ 1.5 6.9 ns CL = 50 pF 4

CAD (KiCad official)

  • Symbol: SN74ABT5402ADWR
  • Footprint: Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm
  • 3D model: SOIC-28-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74abt5402adwr-etched.step / sn74abt5402adwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74abt5402adwr.step / sn74abt5402adwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (13 pp, sha256 7bbf7e402f2a9b66, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF