component
SN74ABT377ADWR
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+56@@ -0,0 +1,56 @@+# SN74ABT377ADWR++**Texas Instruments** · Flip Flops · SOIC-20-300mil++SN74ABT377ADWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLKEN | input | Active-low clock enable input that inhibits data transfer to outputs when high. |+| 2 | 1Q | output | Flip-flop 1 buffered Q output, transfers D data on positive-edge CLK when CLKEN is low. |+| 3 | 1D | input | Flip-flop 1 D data input, captured on positive-edge CLK when CLKEN is low. |+| 4 | 2D | input | Flip-flop 2 D data input, captured on positive-edge CLK when CLKEN is low. |+| 5 | 2Q | output | Flip-flop 2 buffered Q output, transfers D data on positive-edge CLK when CLKEN is low. |+| 6 | 3Q | output | Flip-flop 3 buffered Q output, transfers D data on positive-edge CLK when CLKEN is low. |+| 7 | 3D | input | Flip-flop 3 D data input, captured on positive-edge CLK when CLKEN is low. |+| 8 | 4D | input | Flip-flop 4 D data input, captured on positive-edge CLK when CLKEN is low. |+| 9 | 4Q | output | Flip-flop 4 buffered Q output, transfers D data on positive-edge CLK when CLKEN is low. |+| 10 | GND | power_in | Ground power supply connection. |+| 11 | CLK | input | Positive-edge-triggered clock input for data transfer when CLKEN is low. |+| 12 | 5Q | output | Flip-flop 5 buffered Q output, transfers D data on positive-edge CLK when CLKEN is low. |+| 13 | 5D | input | Flip-flop 5 D data input, captured on positive-edge CLK when CLKEN is low. |+| 14 | 6D | input | Flip-flop 6 D data input, captured on positive-edge CLK when CLKEN is low. |+| 15 | 6Q | output | Flip-flop 6 buffered Q output, transfers D data on positive-edge CLK when CLKEN is low. |+| 16 | 7Q | output | Flip-flop 7 buffered Q output, transfers D data on positive-edge CLK when CLKEN is low. |+| 17 | 7D | input | Flip-flop 7 D data input, captured on positive-edge CLK when CLKEN is low. |+| 18 | 8D | input | Flip-flop 8 D data input, captured on positive-edge CLK when CLKEN is low. |+| 19 | 8Q | output | Flip-flop 8 buffered Q output, transfers D data on positive-edge CLK when CLKEN is low. |+| 20 | VCC | power_in | Supply voltage power connection, recommended operating range 4.5-5.5V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-20-300mil |+| Category | Logic |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `SN74ABT377ADWR`+- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`+- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)+- 3D model files: `sn74abt377adwr-etched.step` / `sn74abt377adwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74abt377adwr.step` / `sn74abt377adwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74abt377a) (25 pp, sha256 `37f5822de8187c3f`, retrieved 2026-10-03, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74abt377adwr-datasheet.pdf)
page.jsonadded+230@@ -0,0 +1,230 @@+{+ "slug": "sn74abt377adwr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74abt377adwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74abt377adwr.kicad_sym",+ "sn74abt377adwr.kicad_mod",+ "sn74abt377adwr.glb",+ "sn74abt377adwr.step",+ "sn74abt377adwr.lbr",+ "docs/hero.png",+ "docs/sn74abt377adwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn74abt377adwr-hero.glb",+ "sn74abt377adwr-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN74ABT377ADWR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-20-300mil",+ "pin_count": 20,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://www.ti.com/cn/lit/gpn/sn74abt377a",+ "parts": {+ "symbol": "sn74abt377adwr.kicad_sym",+ "footprint": "sn74abt377adwr.kicad_mod",+ "model_3d": "sn74abt377adwr-hero.glb",+ "model_3d_plain": "sn74abt377adwr.glb",+ "model_3d_step": "sn74abt377adwr-etched.step",+ "model_3d_step_plain": "sn74abt377adwr.step",+ "lbr": "sn74abt377adwr.lbr"+ },+ "distributor_links": {+ "lcsc": 2677758,+ "digikey": "296-4009-2-ND",+ "mouser": "595-SN74ABT377ADWR"+ },+ "distributor_check": {+ "checked_at": "2026-10-03T09:23:06Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-4009-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-SN74ABT377ADWR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "CLKEN",+ "type": "input",+ "description": "Active-low clock enable input that inhibits data transfer to outputs when high."+ },+ {+ "number": "2",+ "name": "1Q",+ "type": "output",+ "description": "Flip-flop 1 buffered Q output, transfers D data on positive-edge CLK when CLKEN is low."+ },+ {+ "number": "3",+ "name": "1D",+ "type": "input",+ "description": "Flip-flop 1 D data input, captured on positive-edge CLK when CLKEN is low."+ },+ {+ "number": "4",+ "name": "2D",+ "type": "input",+ "description": "Flip-flop 2 D data input, captured on positive-edge CLK when CLKEN is low."+ },+ {+ "number": "5",+ "name": "2Q",+ "type": "output",+ "description": "Flip-flop 2 buffered Q output, transfers D data on positive-edge CLK when CLKEN is low."+ },+ {+ "number": "6",+ "name": "3Q",+ "type": "output",+ "description": "Flip-flop 3 buffered Q output, transfers D data on positive-edge CLK when CLKEN is low."+ },+ {+ "number": "7",+ "name": "3D",+ "type": "input",+ "description": "Flip-flop 3 D data input, captured on positive-edge CLK when CLKEN is low."+ },+ {+ "number": "8",+ "name": "4D",+ "type": "input",+ "description": "Flip-flop 4 D data input, captured on positive-edge CLK when CLKEN is low."+ },+ {+ "number": "9",+ "name": "4Q",+ "type": "output",+ "description": "Flip-flop 4 buffered Q output, transfers D data on positive-edge CLK when CLKEN is low."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground power supply connection."+ },+ {+ "number": "11",+ "name": "CLK",+ "type": "input",+ "description": "Positive-edge-triggered clock input for data transfer when CLKEN is low."+ },+ {+ "number": "12",+ "name": "5Q",+ "type": "output",+ "description": "Flip-flop 5 buffered Q output, transfers D data on positive-edge CLK when CLKEN is low."+ },+ {+ "number": "13",+ "name": "5D",+ "type": "input",+ "description": "Flip-flop 5 D data input, captured on positive-edge CLK when CLKEN is low."+ },+ {+ "number": "14",+ "name": "6D",+ "type": "input",+ "description": "Flip-flop 6 D data input, captured on positive-edge CLK when CLKEN is low."+ },+ {+ "number": "15",+ "name": "6Q",+ "type": "output",+ "description": "Flip-flop 6 buffered Q output, transfers D data on positive-edge CLK when CLKEN is low."+ },+ {+ "number": "16",+ "name": "7Q",+ "type": "output",+ "description": "Flip-flop 7 buffered Q output, transfers D data on positive-edge CLK when CLKEN is low."+ },+ {+ "number": "17",+ "name": "7D",+ "type": "input",+ "description": "Flip-flop 7 D data input, captured on positive-edge CLK when CLKEN is low."+ },+ {+ "number": "18",+ "name": "8D",+ "type": "input",+ "description": "Flip-flop 8 D data input, captured on positive-edge CLK when CLKEN is low."+ },+ {+ "number": "19",+ "name": "8Q",+ "type": "output",+ "description": "Flip-flop 8 buffered Q output, transfers D data on positive-edge CLK when CLKEN is low."+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage power connection, recommended operating range 4.5-5.5V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 25,+ "cost_usd": 0.1397,+ "at": "2026-10-03T09:22:42"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn74abt377a",+ "pages": 25,+ "sha256": "37f5822de8187c3f",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}