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SN74ABT377ADBR

Texas Instruments · Flip Flops · SSOP-20

SN74ABT377ADBR from Texas Instruments, in a SSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKEN input Common clock enable: when low, D data is transferred to Q on the positive-going CLK edge, and when high the flip-flops hold their state; CLKEN transitions are designed not to cause false clocking.
2 1Q output Flip-flop 1 output, rated for -32 mA IOH and 64 mA IOL (high-drive output).
3 1D input Data input for flip-flop 1, which must meet the setup and hold times relative to the positive-going CLK edge.
4 2D input Data input for flip-flop 2, which must meet the setup and hold times relative to the positive-going CLK edge.
5 2Q output Flip-flop 2 output, rated for -32 mA IOH and 64 mA IOL (high-drive output).
6 3Q output Flip-flop 3 output, rated for -32 mA IOH and 64 mA IOL (high-drive output).
7 3D input Data input for flip-flop 3, which must meet the setup and hold times relative to the positive-going CLK edge.
8 4D input Data input for flip-flop 4, which must meet the setup and hold times relative to the positive-going CLK edge.
9 4Q output Flip-flop 4 output, rated for -32 mA IOH and 64 mA IOL (high-drive output).
10 GND power_in Ground reference for the device.
11 CLK input Buffered clock input; the outputs change on the positive-going edge when CLKEN is low, and the CLK high or low level alone has no effect, with a minimum pulse duration of 3.3 ns.
12 5Q output Flip-flop 5 output, rated for -32 mA IOH and 64 mA IOL (high-drive output).
13 5D input Data input for flip-flop 5, which must meet the setup and hold times relative to the positive-going CLK edge.
14 6D input Data input for flip-flop 6, which must meet the setup and hold times relative to the positive-going CLK edge.
15 6Q output Flip-flop 6 output, rated for -32 mA IOH and 64 mA IOL (high-drive output).
16 7Q output Flip-flop 7 output, rated for -32 mA IOH and 64 mA IOL (high-drive output).
17 7D input Data input for flip-flop 7, which must meet the setup and hold times relative to the positive-going CLK edge.
18 8D input Data input for flip-flop 8, which must meet the setup and hold times relative to the positive-going CLK edge.
19 8Q output Flip-flop 8 output, rated for -32 mA IOH and 64 mA IOL (high-drive output).
20 VCC power_in Supply voltage, with a recommended operating range of 4.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Current into any output in the low state IO 128 mA SN74ABT377A 3
Input clamp current IIK -18 mA VI < 0 3
Output clamp current IOK -50 mA VO < 0 3
Supply voltage range VCC -0.5 7 V 3
Input voltage range VI -0.5 7 V see Note 1 3
Voltage range applied to any output in the high or power-off state VO -0.5 5.5 V 3
Storage temperature range Tstg -65 150 °C 3
Package thermal impedance, DB package θJA 115 °C/W DB package, per JESD51 (see Note 2) 3
Supply voltage VCC 4.5 5.5 V 3
High-level input voltage VIH 2 V 3
Low-level input voltage VIL 0.8 V 3
Input voltage VI 0 V maximum is VCC 3
High-level output current IOH -32 mA SN74ABT377A 3
Low-level output current IOL 64 mA SN74ABT377A 3
Input transition rise or fall rate Δt/Δv 5 ns/V Outputs enabled 3
Operating free-air temperature TA -40 85 °C SN74ABT377A 3
Input clamp voltage VIK -1.2 V VCC = 4.5 V, II = -18 mA 4
High-level output voltage VOH 2.5 V VCC = 4.5 V, IOH = -3 mA 4
High-level output voltage VOH 3 V VCC = 5 V, IOH = -3 mA 4
High-level output voltage VOH 2 V VCC = 4.5 V, IOH = -32 mA 4
Low-level output voltage VOL 0.55 V VCC = 4.5 V, IOL = 48 mA 4
Input current II -1 1 µA VCC = 5.5 V, VI = VCC or GND 4
Off-state output current Ioff -100 100 µA VCC = 0, VI or VO ≤ 4.5 V 4
Output high leakage current ICEX 50 µA VCC = 5.5 V, VO = 5.5 V, outputs high 4
Short-circuit output current IO -50 -180 mA VCC = 5.5 V, VO = 2.5 V 4
Supply current ICC 250 µA VCC = 5.5 V, IO = 0, VI = VCC or GND, outputs high 4
Supply current ICC 30 mA VCC = 5.5 V, IO = 0, VI = VCC or GND, outputs low 4
Increase in supply current per input ΔICC 1.5 mA VCC = 5.5 V, one input at 3.4 V, other inputs at VCC or GND 4
Clock frequency fclock 0 150 MHz 5
Pulse duration CLK high or low tw 3.3 ns 5
Setup time before CLK↑, data high or low tsu 2.5 ns 5
Setup time before CLK↑, CLKEN high or low tsu 3 ns 5
Hold time after CLK↑, data high or low th 1.8 ns 5
Hold time after CLK↑, CLKEN high or low th 1.2 ns 5
Maximum clock frequency fmax 150 MHz CL = 50 pF 5
Propagation delay CLK to Q (low-to-high) tPLH 2.2 4.5 6.5 ns CL = 50 pF 5
Propagation delay CLK to Q (high-to-low) tPHL 2.6 5.3 7.3 ns CL = 50 pF 5

CAD (KiCad official)

  • Symbol: SN74ABT377ADBR
  • Footprint: Adom_Gen:Texas_Instruments_SN74
  • 3D model: SSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74abt377adbr-etched.step / sn74abt377adbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74abt377adbr.step / sn74abt377adbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 09c03ca670bdb907, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF