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SN74ABT373DWR

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Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74ABT373DWR

Texas Instruments · Latches · SOIC-20-300mil

SN74ABT373DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Buffered output-enable input; when high, the eight 3-state outputs go to high impedance, and OE should be tied to VCC through a pullup resistor to keep the outputs high-impedance during power up or power down.
2 1Q tri_state 3-state output of latch 1; high-drive output rated for -32 mA IOH and 64 mA IOL.
3 1D input Data input to latch 1; while LE is high, Q follows D, and the data is latched when LE goes low (setup and hold limits apply to the LE falling edge).
4 2D input Data input to latch 2; while LE is high, Q follows D, and the data is latched when LE goes low (setup and hold limits apply to the LE falling edge).
5 2Q tri_state 3-state output of latch 2; high-drive output rated for -32 mA IOH and 64 mA IOL.
6 3Q tri_state 3-state output of latch 3; high-drive output rated for -32 mA IOH and 64 mA IOL.
7 3D input Data input to latch 3; while LE is high, Q follows D, and the data is latched when LE goes low (setup and hold limits apply to the LE falling edge).
8 4D input Data input to latch 4; while LE is high, Q follows D, and the data is latched when LE goes low (setup and hold limits apply to the LE falling edge).
9 4Q tri_state 3-state output of latch 4; high-drive output rated for -32 mA IOH and 64 mA IOL.
10 GND power_in Device ground reference.
11 LE input Latch-enable input; while high the Q outputs follow the D inputs, and when taken low the Q outputs are latched at the D levels.
12 5Q tri_state 3-state output of latch 5; high-drive output rated for -32 mA IOH and 64 mA IOL.
13 5D input Data input to latch 5; while LE is high, Q follows D, and the data is latched when LE goes low (setup and hold limits apply to the LE falling edge).
14 6D input Data input to latch 6; while LE is high, Q follows D, and the data is latched when LE goes low (setup and hold limits apply to the LE falling edge).
15 6Q tri_state 3-state output of latch 6; high-drive output rated for -32 mA IOH and 64 mA IOL.
16 7Q tri_state 3-state output of latch 7; high-drive output rated for -32 mA IOH and 64 mA IOL.
17 7D input Data input to latch 7; while LE is high, Q follows D, and the data is latched when LE goes low (setup and hold limits apply to the LE falling edge).
18 8D input Data input to latch 8; while LE is high, Q follows D, and the data is latched when LE goes low (setup and hold limits apply to the LE falling edge).
19 8Q tri_state 3-state output of latch 8; high-drive output rated for -32 mA IOH and 64 mA IOL.
20 VCC power_in Supply voltage; recommended range 4.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74ABT373DWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74abt373dwr-etched.step / sn74abt373dwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74abt373dwr.step / sn74abt373dwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 5eeda3a5c21d60b3, retrieved 2026-10-10, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF