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SN74ABT273PWRE4

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Texas Instruments Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Contents

README

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SN74ABT273PWRE4

Texas Instruments · Flip Flops · TSSOP-20

SN74ABT273PWRE4 from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Asynchronous clear input (active low); forces all Q outputs low when held low.
2 1Q output Q output of flip-flop 1; state changes on positive edge of CLK when CLR is high.
3 1D input Data input of flip-flop 1; sampled on positive edge of CLK when CLR is high.
4 2D input Data input of flip-flop 2; sampled on positive edge of CLK when CLR is high.
5 2Q output Q output of flip-flop 2; state changes on positive edge of CLK when CLR is high.
6 3Q output Q output of flip-flop 3; state changes on positive edge of CLK when CLR is high.
7 3D input Data input of flip-flop 3; sampled on positive edge of CLK when CLR is high.
8 4D input Data input of flip-flop 4; sampled on positive edge of CLK when CLR is high.
9 4Q output Q output of flip-flop 4; state changes on positive edge of CLK when CLR is high.
10 GND power_in Ground connection; negative supply rail.
11 CLK input Clock input (positive-edge triggered); rising edge transfers D data to Q outputs when CLR is high.
12 5Q output Q output of flip-flop 5; state changes on positive edge of CLK when CLR is high.
13 5D input Data input of flip-flop 5; sampled on positive edge of CLK when CLR is high.
14 6D input Data input of flip-flop 6; sampled on positive edge of CLK when CLR is high.
15 6Q output Q output of flip-flop 6; state changes on positive edge of CLK when CLR is high.
16 7Q output Q output of flip-flop 7; state changes on positive edge of CLK when CLR is high.
17 7D input Data input of flip-flop 7; sampled on positive edge of CLK when CLR is high.
18 8D input Data input of flip-flop 8; sampled on positive edge of CLK when CLR is high.
19 8Q output Q output of flip-flop 8; state changes on positive edge of CLK when CLR is high.
20 VCC power_in Supply voltage connection (4.5 V to 5.5 V); positive supply rail.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74ABT273PWRE4
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74abt273pwre4-etched.step / sn74abt273pwre4-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74abt273pwre4.step / sn74abt273pwre4.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 e91a86156f04d0ec, retrieved 2026-09-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF