component
SN74ABT273DBR
Public Made by Adomby adom
Texas Instruments Flip Flops, SSOP-20-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
SN74ABT273DBR
Texas Instruments · Flip Flops · SSOP-20-208mil
SN74ABT273DBR from Texas Instruments, in a SSOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLR | input | Active-low direct clear; when low, all Q outputs are forced low regardless of CLK or D. |
| 2 | 1Q | output | Q output of flip-flop 1; high-drive output rated for -32 mA IOH and 64 mA IOL. |
| 3 | 1D | input | Data input of flip-flop 1; must meet setup and hold times relative to the positive-going CLK edge. |
| 4 | 2D | input | Data input of flip-flop 2; must meet setup and hold times relative to the positive-going CLK edge. |
| 5 | 2Q | output | Q output of flip-flop 2; high-drive output rated for -32 mA IOH and 64 mA IOL. |
| 6 | 3Q | output | Q output of flip-flop 3; high-drive output rated for -32 mA IOH and 64 mA IOL. |
| 7 | 3D | input | Data input of flip-flop 3; must meet setup and hold times relative to the positive-going CLK edge. |
| 8 | 4D | input | Data input of flip-flop 4; must meet setup and hold times relative to the positive-going CLK edge. |
| 9 | 4Q | output | Q output of flip-flop 4; high-drive output rated for -32 mA IOH and 64 mA IOL. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | CLK | input | Clock input; D is transferred to Q on the positive-going edge and has no effect while CLK is high or low. |
| 12 | 5Q | output | Q output of flip-flop 5; high-drive output rated for -32 mA IOH and 64 mA IOL. |
| 13 | 5D | input | Data input of flip-flop 5; must meet setup and hold times relative to the positive-going CLK edge. |
| 14 | 6D | input | Data input of flip-flop 6; must meet setup and hold times relative to the positive-going CLK edge. |
| 15 | 6Q | output | Q output of flip-flop 6; high-drive output rated for -32 mA IOH and 64 mA IOL. |
| 16 | 7Q | output | Q output of flip-flop 7; high-drive output rated for -32 mA IOH and 64 mA IOL. |
| 17 | 7D | input | Data input of flip-flop 7; must meet setup and hold times relative to the positive-going CLK edge. |
| 18 | 8D | input | Data input of flip-flop 8; must meet setup and hold times relative to the positive-going CLK edge. |
| 19 | 8Q | output | Q output of flip-flop 8; high-drive output rated for -32 mA IOH and 64 mA IOL. |
| 20 | VCC | power_in | Supply voltage; recommended operating range 4.5 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SSOP-20-208mil |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
SN74ABT273DBR - Footprint:
Package_SO:SSOP-20_5.3x7.2mm_P0.65mm - 3D model: SSOP-20-208mil (KiCad packages3D, STEP)
- 3D model files:
sn74abt273dbr-etched.step/sn74abt273dbr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74abt273dbr.step/sn74abt273dbr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (26 pp, sha256
60de3f9efa6292e1, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74ABT273DBR
**Texas Instruments** · Flip Flops · SSOP-20-208mil
SN74ABT273DBR from Texas Instruments, in a SSOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLR | input | Active-low direct clear; when low, all Q outputs are forced low regardless of CLK or D. |
| 2 | 1Q | output | Q output of flip-flop 1; high-drive output rated for -32 mA IOH and 64 mA IOL. |
| 3 | 1D | input | Data input of flip-flop 1; must meet setup and hold times relative to the positive-going CLK edge. |
| 4 | 2D | input | Data input of flip-flop 2; must meet setup and hold times relative to the positive-going CLK edge. |
| 5 | 2Q | output | Q output of flip-flop 2; high-drive output rated for -32 mA IOH and 64 mA IOL. |
| 6 | 3Q | output | Q output of flip-flop 3; high-drive output rated for -32 mA IOH and 64 mA IOL. |
| 7 | 3D | input | Data input of flip-flop 3; must meet setup and hold times relative to the positive-going CLK edge. |
| 8 | 4D | input | Data input of flip-flop 4; must meet setup and hold times relative to the positive-going CLK edge. |
| 9 | 4Q | output | Q output of flip-flop 4; high-drive output rated for -32 mA IOH and 64 mA IOL. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | CLK | input | Clock input; D is transferred to Q on the positive-going edge and has no effect while CLK is high or low. |
| 12 | 5Q | output | Q output of flip-flop 5; high-drive output rated for -32 mA IOH and 64 mA IOL. |
| 13 | 5D | input | Data input of flip-flop 5; must meet setup and hold times relative to the positive-going CLK edge. |
| 14 | 6D | input | Data input of flip-flop 6; must meet setup and hold times relative to the positive-going CLK edge. |
| 15 | 6Q | output | Q output of flip-flop 6; high-drive output rated for -32 mA IOH and 64 mA IOL. |
| 16 | 7Q | output | Q output of flip-flop 7; high-drive output rated for -32 mA IOH and 64 mA IOL. |
| 17 | 7D | input | Data input of flip-flop 7; must meet setup and hold times relative to the positive-going CLK edge. |
| 18 | 8D | input | Data input of flip-flop 8; must meet setup and hold times relative to the positive-going CLK edge. |
| 19 | 8Q | output | Q output of flip-flop 8; high-drive output rated for -32 mA IOH and 64 mA IOL. |
| 20 | VCC | power_in | Supply voltage; recommended operating range 4.5 V to 5.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SSOP-20-208mil |
| Category | Logic |
| Pins | 20 |
## CAD (KiCad official)
- Symbol: `SN74ABT273DBR`
- Footprint: `Package_SO:SSOP-20_5.3x7.2mm_P0.65mm`
- 3D model: SSOP-20-208mil (KiCad packages3D, STEP)
- 3D model files: `sn74abt273dbr-etched.step` / `sn74abt273dbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74abt273dbr.step` / `sn74abt273dbr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74abt273) (26 pp, sha256 `60de3f9efa6292e1`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74abt273dbr-datasheet.pdf)