component

SN74ABT240ANSR

Public Made by Adom

by adom

Texas Instruments Buffers, Drivers, Receivers, Transceivers, SOIC-20-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74abt240ansrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 12d ago
viewers sn74abt240ansr: viewers · Ray 12d ago
package.json Publish 0.1.0 · Ray 12d ago
page.json Set visibility: public · Ray 12d ago
README.md Publish 0.1.0 · Ray 12d ago
sn74abt240ansr-etched.glb sn74abt240ansr: factory component page (tier=lcsc) · Ray 12d ago
sn74abt240ansr-etched.step sn74abt240ansr: factory component page (tier=lcsc) · Ray 12d ago
sn74abt240ansr-hero.glb sn74abt240ansr: hero GLB from the etched model (keeps the MPN mark) · Ray 12d ago
sn74abt240ansr-hero.overlay.json Publish 0.1.0 · Ray 12d ago
sn74abt240ansr.glb Publish 0.1.0 · Ray 12d ago
sn74abt240ansr.kicad_mod Publish 0.1.0 · Ray 12d ago
sn74abt240ansr.kicad_sym Publish 0.1.0 · Ray 12d ago
sn74abt240ansr.lbr Publish 0.1.0 · Ray 12d ago
sn74abt240ansr.step Publish 0.1.0 · Ray 12d ago

SN74ABT240ANSR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SOIC-20-208mil

SN74ABT240ANSR from Texas Instruments, in a SOIC-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Active-low output enable for buffers 1A/1Y; when OE is high the 1Y outputs are in the high-impedance state, and OE should be tied to VCC through a pullup resistor to hold high-impedance during power up or power down.
2 1A1 input Data input of buffer 1, passed inverted to output 1Y1 when 1OE is low; unused inputs must be held at VCC or GND.
3 2Y4 tri_state Inverting 3-state output of buffer 2 (channel 4), enabled when 2OE is low and high-impedance when 2OE is high.
4 1A2 input Data input of buffer 1, passed inverted to output 1Y2 when 1OE is low; unused inputs must be held at VCC or GND.
5 2Y3 tri_state Inverting 3-state output of buffer 2 (channel 3), enabled when 2OE is low and high-impedance when 2OE is high.
6 1A3 input Data input of buffer 1, passed inverted to output 1Y3 when 1OE is low; unused inputs must be held at VCC or GND.
7 2Y2 tri_state Inverting 3-state output of buffer 2 (channel 2), enabled when 2OE is low and high-impedance when 2OE is high.
8 1A4 input Data input of buffer 1, passed inverted to output 1Y4 when 1OE is low; unused inputs must be held at VCC or GND.
9 2Y1 tri_state Inverting 3-state output of buffer 2 (channel 1), enabled when 2OE is low and high-impedance when 2OE is high.
10 GND power_in Ground reference for the device; the recommended supply range is 4.5 V to 5.5 V on VCC.
11 2A1 input Data input of buffer 2, passed inverted to output 2Y1 when 2OE is low; unused inputs must be held at VCC or GND.
12 1Y4 tri_state Inverting 3-state output of buffer 1 (channel 4), enabled when 1OE is low and high-impedance when 1OE is high.
13 2A2 input Data input of buffer 2, passed inverted to output 2Y2 when 2OE is low; unused inputs must be held at VCC or GND.
14 1Y3 tri_state Inverting 3-state output of buffer 1 (channel 3), enabled when 1OE is low and high-impedance when 1OE is high.
15 2A3 input Data input of buffer 2, passed inverted to output 2Y3 when 2OE is low; unused inputs must be held at VCC or GND.
16 1Y2 tri_state Inverting 3-state output of buffer 1 (channel 2), enabled when 1OE is low and high-impedance when 1OE is high.
17 2A4 input Data input of buffer 2, passed inverted to output 2Y4 when 2OE is low; unused inputs must be held at VCC or GND.
18 1Y1 tri_state Inverting 3-state output of buffer 1 (channel 1), enabled when 1OE is low and high-impedance when 1OE is high.
19 2OE input Active-low output enable for buffers 2A/2Y; when OE is high the 2Y outputs are in the high-impedance state, and OE should be tied to VCC through a pullup resistor to hold high-impedance during power up or power down.
20 VCC power_in Supply voltage, specified from 4.5 V to 5.5 V for the SN74ABT240A.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-208mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74ABT240ANSR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-208mil (KiCad packages3D, STEP)
  • 3D model files: sn74abt240ansr-etched.step / sn74abt240ansr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74abt240ansr.step / sn74abt240ansr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 809f246e9ce5e1ce, retrieved 2026-10-10, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF