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SN74ABT240ADWR

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Texas Instruments Buffers, Drivers, Receivers, Transceivers, SOIC-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74ABT240ADWR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SOIC-20

SN74ABT240ADWR from Texas Instruments, in a SOIC-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Active-low output enable for buffers 1Y1 to 1Y4; when high, outputs 1Y1 to 1Y4 are forced to the high-impedance state.
2 1A1 input Data input to buffer 1; when 1OE is low, the inverted data appears on 1Y1, and unused inputs must be held at VCC or GND.
3 2Y4 tri_state 3-state output of buffer 2 (channel 4), inverted from 2A4 when 2OE is low and high-impedance when 2OE is high.
4 1A2 input Data input to buffer 1 (channel 2), inverted to 1Y2 when 1OE is low; unused inputs must be held at VCC or GND.
5 2Y3 tri_state 3-state output of buffer 2 (channel 3), inverted from 2A3 when 2OE is low and high-impedance when 2OE is high.
6 1A3 input Data input to buffer 1 (channel 3), inverted to 1Y3 when 1OE is low; unused inputs must be held at VCC or GND.
7 2Y2 tri_state 3-state output of buffer 2 (channel 2), inverted from 2A2 when 2OE is low and high-impedance when 2OE is high.
8 1A4 input Data input to buffer 1 (channel 4), inverted to 1Y4 when 1OE is low; unused inputs must be held at VCC or GND.
9 2Y1 tri_state 3-state output of buffer 2 (channel 1), inverted from 2A1 when 2OE is low and high-impedance when 2OE is high.
10 GND power_in Device ground reference.
11 2A1 input Data input to buffer 2 (channel 1), inverted to 2Y1 when 2OE is low; unused inputs must be held at VCC or GND.
12 1Y4 tri_state 3-state output of buffer 1 (channel 4), inverted from 1A4 when 1OE is low and high-impedance when 1OE is high.
13 2A2 input Data input to buffer 2 (channel 2), inverted to 2Y2 when 2OE is low; unused inputs must be held at VCC or GND.
14 1Y3 tri_state 3-state output of buffer 1 (channel 3), inverted from 1A3 when 1OE is low and high-impedance when 1OE is high.
15 2A3 input Data input to buffer 2 (channel 3), inverted to 2Y3 when 2OE is low; unused inputs must be held at VCC or GND.
16 1Y2 tri_state 3-state output of buffer 1 (channel 2), inverted from 1A2 when 1OE is low and high-impedance when 1OE is high.
17 2A4 input Data input to buffer 2 (channel 4), inverted to 2Y4 when 2OE is low; unused inputs must be held at VCC or GND.
18 1Y1 tri_state 3-state output of buffer 1 (channel 1), inverted from 1A1 when 1OE is low and high-impedance when 1OE is high.
19 2OE input Active-low output enable for buffers 2Y1 to 2Y4; when high, outputs 2Y1 to 2Y4 are forced to the high-impedance state.
20 VCC power_in Supply voltage, 4.5 V to 5.5 V recommended; OE should be tied to VCC through a pullup resistor to hold outputs high-impedance during power up or down.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74ABT240ADWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20 (KiCad packages3D, STEP)
  • 3D model files: sn74abt240adwr-etched.step / sn74abt240adwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74abt240adwr.step / sn74abt240adwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 809f246e9ce5e1ce, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF