component
SN7425N
Public Made by Adomby adom
Texas Instruments Gates, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN7425N
Texas Instruments · Gates · PDIP-14
SN7425N from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1 data input A; high-level input voltage at least 2 V and low-level at most 0.8 V. |
| 2 | 1B | input | Gate 1 data input B; high-level input voltage at least 2 V and low-level at most 0.8 V. |
| 3 | 1G | input | Gate 1 strobe input G; output 1Y is forced high when G is low. |
| 4 | 1C | input | Gate 1 data input C; high-level input voltage at least 2 V and low-level at most 0.8 V. |
| 5 | 1D | input | Gate 1 data input D; high-level input voltage at least 2 V and low-level at most 0.8 V. |
| 6 | 1Y | output | Gate 1 output Y = NOT[G(A+B+C+D)], rated for 16 mA low-level and -0.8 mA high-level output current. |
| 7 | GND | power_in | Ground (network ground terminal), reference for all voltages. |
| 8 | 2Y | output | Gate 2 output Y = NOT[G(A+B+C+D)], rated for 16 mA low-level and -0.8 mA high-level output current. |
| 9 | 2A | input | Gate 2 data input A; high-level input voltage at least 2 V and low-level at most 0.8 V. |
| 10 | 2B | input | Gate 2 data input B; high-level input voltage at least 2 V and low-level at most 0.8 V. |
| 11 | 2G | input | Gate 2 strobe input G; output 2Y is forced high when G is low. |
| 12 | 2C | input | Gate 2 data input C; high-level input voltage at least 2 V and low-level at most 0.8 V. |
| 13 | 2D | input | Gate 2 data input D; high-level input voltage at least 2 V and low-level at most 0.8 V. |
| 14 | VCC | power_in | Supply voltage, 4.75 V to 5.25 V recommended for the 74 family, 7 V absolute maximum. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Logic ICs |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN7425N - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files:
sn7425n-etched.step/sn7425n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn7425n.step/sn7425n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (19 pp, sha256
6f348fc7e717c020, retrieved 2026-10-31, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN7425N
**Texas Instruments** · Gates · PDIP-14
SN7425N from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1 data input A; high-level input voltage at least 2 V and low-level at most 0.8 V. |
| 2 | 1B | input | Gate 1 data input B; high-level input voltage at least 2 V and low-level at most 0.8 V. |
| 3 | 1G | input | Gate 1 strobe input G; output 1Y is forced high when G is low. |
| 4 | 1C | input | Gate 1 data input C; high-level input voltage at least 2 V and low-level at most 0.8 V. |
| 5 | 1D | input | Gate 1 data input D; high-level input voltage at least 2 V and low-level at most 0.8 V. |
| 6 | 1Y | output | Gate 1 output Y = NOT[G(A+B+C+D)], rated for 16 mA low-level and -0.8 mA high-level output current. |
| 7 | GND | power_in | Ground (network ground terminal), reference for all voltages. |
| 8 | 2Y | output | Gate 2 output Y = NOT[G(A+B+C+D)], rated for 16 mA low-level and -0.8 mA high-level output current. |
| 9 | 2A | input | Gate 2 data input A; high-level input voltage at least 2 V and low-level at most 0.8 V. |
| 10 | 2B | input | Gate 2 data input B; high-level input voltage at least 2 V and low-level at most 0.8 V. |
| 11 | 2G | input | Gate 2 strobe input G; output 2Y is forced high when G is low. |
| 12 | 2C | input | Gate 2 data input C; high-level input voltage at least 2 V and low-level at most 0.8 V. |
| 13 | 2D | input | Gate 2 data input D; high-level input voltage at least 2 V and low-level at most 0.8 V. |
| 14 | VCC | power_in | Supply voltage, 4.75 V to 5.25 V recommended for the 74 family, 7 V absolute maximum. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Logic ICs |
| Pins | 14 |
## CAD (KiCad official)
- Symbol: `SN7425N`
- Footprint: `Package_DIP:DIP-14_W7.62mm`
- 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files: `sn7425n-etched.step` / `sn7425n-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn7425n.step` / `sn7425n.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](docs/sn7425n-datasheet.pdf) (19 pp, sha256 `6f348fc7e717c020`, retrieved 2026-10-31, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn7425n-datasheet.pdf)