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SN65MLVD204ADR

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Texas Instruments LVDS ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterfacesn65mlvd204adrfactory-2.0.0extractor-text

Verified SN65MLVD204ADR

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: SN65MLVD204ADR · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 42-page datasheet
  • ✓distributor: lcsc C2671165, digikey 296-39191-2-ND, mouser 595-SN65MLVD204ADR
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-kwivjb6u/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ sn65mlvd204adr.kicad_sym✓ sn65mlvd204adr.kicad_mod✓ sn65mlvd204adr.step
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SN65MLVD204ADR

Texas Instruments · LVDS ICs · SOIC-8

SN65MLVD204ADR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 R output Receiver output.
2 RE input Receiver enable pin: High = Disable, Low = Enable.
3 DE input Driver enable pin: High = Enable, Low = Disable.
4 D input Driver input.
5 GND power_in Power supply ground.
6 A bidirectional Differential I/O bus pin; recommended voltage at any bus terminal is -1.4 V to 3.8 V, with absolute limits of -1.8 V to 4 V for this device.
7 B bidirectional Differential I/O bus pin; recommended voltage at any bus terminal is -1.4 V to 3.8 V, with absolute limits of -1.8 V to 4 V for this device.
8 VCC power_in Power supply, 3.3 V nominal with a recommended range of 3 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Interface
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 4 V 4
Input voltage D, DE, RE VI -0.5 4 V 4
Input voltage A, B (SN65MLVD204A) VI -1.8 4 V 4
Output voltage range R VO -0.3 4 V 4
Output voltage range Y, Z, A, or B VO -1.8 4 V 4
Storage temperature Tstg -65 150 °C 4
Supply voltage VCC 3 3.3 3.6 V 4
High-level input voltage VIH 2 V maximum is VCC 4
Low-level input voltage VIL 0.8 V minimum is GND 4
Voltage at any bus terminal VA, VB, VY, VZ -1.4 3.8 V 4
Differential load resistance RL 30 50 Ω 4
Signaling rate 1/tUI 100 Mbps 4
Operating free-air temperature TA -40 85 °C 4
Supply current, driver only ICC 13 22 mA RE and DE at VCC, RL = 50 Ω, All others open 5
Supply current, both disabled ICC 1 4 mA RE at VCC, DE at 0 V, RL = No Load, All others open 5
Supply current, both enabled ICC 16 24 mA RE at 0 V, DE at VCC, RL = 50 Ω, All others open 5
Supply current, receiver only ICC 4 13 mA RE at 0 V, DE at 0 V, All others open 5
Differential output voltage magnitude /VAB/ or /VYZ/ 480 650 mV See Figure 7-2 5
Change in differential output voltage magnitude between logic states Δ/VAB/ or Δ/VYZ/ -50 50 mV 5
Steady-state common-mode output voltage VOS(SS) 0.8 1.2 V See Figure 7-3 5
Change in steady-state common-mode output voltage between logic states ΔVOS(SS) -50 50 mV 5
Peak-to-peak common-mode output voltage VOS(PP) 150 mV 5
Maximum steady-state open-circuit output voltage VY(OC) or VA(OC) 0 2.4 V See Figure 7-7 5
Voltage overshoot, low-to-high level output VP(H) 1.2 VSS See Figure 7-5 5
Voltage overshoot, high-to-low level output VP(L) -0.2 VSS See Figure 7-5 5
High-level input current (D, DE) IIH 0 10 µA VIH = 2 V to VCC 5
Low-level input current (D, DE) IIL 0 10 µA VIL = GND to 0.8 V 5
Differential short-circuit output current magnitude /IOS/ 24 mA See Figure 6-4 5
High-impedance state output current (driver only) IOZ -15 10 µA -1.4 V ≤ (VY or VZ) ≤ 3.8 V, Other output = 1.2 V 5
Power-off output current IO(OFF) -10 10 µA -1.4 V ≤ (VY or VZ) ≤ 3.8 V, Other output = 1.2 V, 0 V ≤ VCC≤ 1.5 V 5
Output capacitance balance, (CY/CZ) CY/Z 0.99 1.01 6
Differential output signal rise time tr 2 2.6 3.2 ns See Figure 7-5 7
Differential output signal fall time tf 2 2.6 3.2 ns See Figure 7-5 7
Propagation delay time, low-to-high-level output tpLH 2 2.5 3.5 ns See Figure 7-5 7
Propagation delay time, high-to-low-level output tpHL 2 2.5 3.5 ns See Figure 7-5 7
Part-to-part skew tsk(pp) 0.9 ns Driver part-to-part skew 7
High-level output voltage (R) VOH 2.4 V IOH = -8 mA 6
Low-level output voltage (R) VOL 0.4 V IOL = 8 mA 6
High-level input current (RE) IIH -10 0 µA VIH = 2 V to VCC 6
Low-level input current (RE) IIL -10 0 µA VIL = GND to 0.8 V 6
High-impedance output current (R) IOZ -10 15 µA VO = 0 V or 3.6 V 6
Input capacitance balance, (CA/CB) CA/B 0.99 1.01 6
Receiver or transceiver with driver disabled input current IA 0 32 µA VA = 3.8 V, VB = 1.2 V 6
Receiver or transceiver with driver disabled input current IA -20 20 µA VA = 0 V or 2.4 V, VB = 1.2 V 6
Receiver or transceiver with driver disabled input current IA -32 0 µA VA = -1.4 V, VB = 1.2 V 6
Receiver or transceiver with driver disabled differential input current (IA, IB) IAB -4 4 µA VA = VB, 1.4 ≤ VA ≤ 3.8 V 6
Receiver or transceiver power-off input current IA(OFF) 0 32 µA VA = 3.8 V, VB = 1.2 V, 0 V ≤ VCC ≤ 1.5 V 6
Receiver or transceiver power-off input current IA(OFF) -20 20 µA VA = 0 V or 2.4 V, VB = 1.2 V, 0 V ≤ VCC ≤ 1.5 V 6
Receiver or transceiver power-off input current IA(OFF) -32 0 µA VA = -1.4 V, VB = 1.2 V, 0 V ≤ VCC ≤ 1.5 V 6
Propagation delay time, low-to-high-level output tPLH 2 3.6 6 ns CL = 15 pF, See Figure 7-10 7
Propagation delay time, high-to-low-level output tPHL 2 3.6 6 ns CL = 15 pF, See Figure 7-10 7
Part-to-part skew tsk(pp) 1 ns Receiver part-to-part skew 7
Junction-to-ambient thermal resistance RθJA 103.9 °C/W D (SOIC) 8 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 50.6 °C/W D (SOIC) 8 pins 5
Junction-to-board thermal resistance RθJB 44.5 °C/W D (SOIC) 8 pins 5

CAD (KiCad official)

  • Symbol: SN65MLVD204ADR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: sn65mlvd204adr-etched.step / sn65mlvd204adr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65mlvd204adr.step / sn65mlvd204adr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (42 pp, sha256 7a0e2e37b09cf486, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF