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SN65MLVD048RGZR

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Texas Instruments LVDS ICs, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN65MLVD048RGZR

Texas Instruments · LVDS ICs · VQFN-48-EP(7x7)

SN65MLVD048RGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected Not connected.
2 VCC power_in Supply voltage (3V to 3.6V recommended); all VCC pins must be connected to supply.
3 2A bidirectional Channel 2 M-LVDS bus non-inverting input/output.
4 2B bidirectional Channel 2 M-LVDS bus inverting input/output.
5 NC unconnected Not connected.
6 GND power_in Circuit ground; all GND pins must be connected to ground.
7 GND power_in Circuit ground; all GND pins must be connected to ground.
8 NC unconnected Not connected.
9 3A bidirectional Channel 3 M-LVDS bus non-inverting input/output.
10 3B bidirectional Channel 3 M-LVDS bus inverting input/output.
11 VCC power_in Supply voltage (3V to 3.6V recommended); all VCC pins must be connected to supply.
12 NC unconnected Not connected.
13 4A bidirectional Channel 4 M-LVDS bus non-inverting input/output.
14 4B bidirectional Channel 4 M-LVDS bus inverting input/output.
15 VCC power_in Supply voltage (3V to 3.6V recommended); all VCC pins must be connected to supply.
16 VCC power_in Supply voltage (3V to 3.6V recommended); all VCC pins must be connected to supply.
17 NC unconnected Not connected.
18 GND power_in Circuit ground; all GND pins must be connected to ground.
19 3RE input Channel 3 receiver enable, active low; internally pulled to logic HIGH (receiver disabled) when left floating.
20 3FSEN input Channel 3 failsafe enable: L selects Type 1 receiver inputs, H selects Type 2; internally pulled HIGH when floating.
21 4RE input Channel 4 receiver enable, active low; internally pulled to logic HIGH (receiver disabled) when left floating.
22 4FSEN input Channel 4 failsafe enable: L selects Type 1 receiver inputs, H selects Type 2; internally pulled HIGH when floating.
23 GND power_in Circuit ground; all GND pins must be connected to ground.
24 VCC power_in Supply voltage (3V to 3.6V recommended); all VCC pins must be connected to supply.
25 NC unconnected Not connected.
26 4R output Channel 4 receiver data output.
27 GND power_in Circuit ground; all GND pins must be connected to ground.
28 NC unconnected Not connected.
29 3R output Channel 3 receiver data output.
30 PDN input Power down: HIGH powers the device up, LOW overrides all other controls and powers down with all outputs Hi-Z; internally pulled LOW when floating.
31 GND power_in Circuit ground; all GND pins must be connected to ground.
32 NC unconnected Not connected.
33 2R output Channel 2 receiver data output.
34 GND power_in Circuit ground; all GND pins must be connected to ground.
35 NC unconnected Not connected.
36 1R output Channel 1 receiver data output.
37 VCC power_in Supply voltage (3V to 3.6V recommended); all VCC pins must be connected to supply.
38 GND power_in Circuit ground; all GND pins must be connected to ground.
39 1FSEN input Channel 1 failsafe enable: L selects Type 1 receiver inputs, H selects Type 2; internally pulled HIGH when floating.
40 1RE input Channel 1 receiver enable, active low; internally pulled to logic HIGH (receiver disabled) when left floating.
41 2FSEN input Channel 2 failsafe enable: L selects Type 1 receiver inputs, H selects Type 2; internally pulled HIGH when floating.
42 2RE input Channel 2 receiver enable, active low; internally pulled to logic HIGH (receiver disabled) when left floating.
43 GND power_in Circuit ground; all GND pins must be connected to ground.
44 NC unconnected Not connected; internal TI test pin that must be left unconnected.
45 VCC power_in Supply voltage (3V to 3.6V recommended); all VCC pins must be connected to supply.
46 VCC power_in Supply voltage (3V to 3.6V recommended); all VCC pins must be connected to supply.
47 1A bidirectional Channel 1 M-LVDS bus non-inverting input/output.
48 1B bidirectional Channel 1 M-LVDS bus inverting input/output.
49 EP power_in PowerPAD exposed thermal pad, connected to GND and must be soldered to the board.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Interface
Pins 49

CAD (KiCad official)

  • Symbol: SN65MLVD048RGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: sn65mlvd048rgzr-etched.step / sn65mlvd048rgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65mlvd048rgzr.step / sn65mlvd048rgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 c68aa86e827f9fcd, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF