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SN65MLVD047PWR

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Texas Instruments LVDS ICs, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN65MLVD047PWR

Texas Instruments · LVDS ICs · TSSOP-16

SN65MLVD047PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Active-high driver enable; the drivers are enabled only when EN = VCC and EN = GND, and the Y and Z outputs go high impedance when EN is low (Device Function Table).
2 1A input LVTTL driver input for channel 1 with VIH of 2 V min to VCC and VIL of 0.8 V max, and a built-in 360-kΩ pull-down.
3 2A input LVTTL driver input for channel 2 with VIH of 2 V min to VCC and VIL of 0.8 V max, and a built-in 360-kΩ pull-down.
4 VCC power_in Single 3.3-V supply pin with a recommended range of 3 V to 3.6 V and an absolute maximum of 4 V.
5 GND power_in Circuit ground reference; all voltages except the differential bus voltages are referenced to this terminal.
6 3A input LVTTL driver input for channel 3 with VIH of 2 V min to VCC and VIL of 0.8 V max, and a built-in 360-kΩ pull-down.
7 4A input LVTTL driver input for channel 4 with VIH of 2 V min to VCC and VIL of 0.8 V max, and a built-in 360-kΩ pull-down.
8 EN input Active-low driver enable (printed with an overbar); the driver is disabled when this pin is high or open, and enabled only when it is low together with EN high.
9 4Z output Inverting M-LVDS driver output of channel 4, with differential output magnitude of 480 to 650 mV into a 30 to 55 Ω load and 9 kV HBM ESD protection on bus pins.
10 4Y output Non-inverting M-LVDS driver output of channel 4, with differential output magnitude of 480 to 650 mV into a 30 to 55 Ω load and bus voltage limits of -1.4 V to 3.8 V.
11 3Y output Non-inverting M-LVDS driver output of channel 3, with differential output magnitude of 480 to 650 mV into a 30 to 55 Ω load and bus voltage limits of -1.4 V to 3.8 V.
12 3Z output Inverting M-LVDS driver output of channel 3, with differential output magnitude of 480 to 650 mV into a 30 to 55 Ω load and 9 kV HBM ESD protection on bus pins.
13 2Z output Inverting M-LVDS driver output of channel 2, with differential output magnitude of 480 to 650 mV into a 30 to 55 Ω load and 9 kV HBM ESD protection on bus pins.
14 2Y output Non-inverting M-LVDS driver output of channel 2, with differential output magnitude of 480 to 650 mV into a 30 to 55 Ω load and bus voltage limits of -1.4 V to 3.8 V.
15 1Y output Non-inverting M-LVDS driver output of channel 1, with differential output magnitude of 480 to 650 mV into a 30 to 55 Ω load and bus voltage limits of -1.4 V to 3.8 V.
16 1Z output Inverting M-LVDS driver output of channel 1, with differential output magnitude of 480 to 650 mV into a 30 to 55 Ω load and 9 kV HBM ESD protection on bus pins.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Interface
Pins 16

CAD (KiCad official)

  • Symbol: SN65MLVD047PWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: sn65mlvd047pwr-etched.step / sn65mlvd047pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65mlvd047pwr.step / sn65mlvd047pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 0e7e8558fd435b2d, retrieved 2026-10-10, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF