component

SN65LVPE502ARGER

Public Made by Adom

by adom

Texas Instruments USB Converters, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterfacesn65lvpe502argerfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 3d ago
viewers sn65lvpe502arger: viewers · Ray 3d ago
package.json Publish 0.1.0 · Ray 3d ago
page.json Set visibility: public · Ray 3d ago
README.md Initial commit: component/sn65lvpe502arger · Ray 3d ago
sn65lvpe502arger-etched.glb sn65lvpe502arger: factory component page (tier=lcsc) · Ray 3d ago
sn65lvpe502arger-etched.step sn65lvpe502arger: factory component page (tier=lcsc) · Ray 3d ago
sn65lvpe502arger-hero.glb Publish 0.1.0 · Ray 3d ago
sn65lvpe502arger-hero.overlay.json Publish 0.1.0 · Ray 3d ago
sn65lvpe502arger.glb Publish 0.1.0 · Ray 3d ago
sn65lvpe502arger.kicad_mod Publish 0.1.0 · Ray 3d ago
sn65lvpe502arger.kicad_sym Publish 0.1.0 · Ray 3d ago
sn65lvpe502arger.lbr Publish 0.1.0 · Ray 3d ago
sn65lvpe502arger.step Publish 0.1.0 · Ray 3d ago

SN65LVPE502ARGER

Texas Instruments · USB Converters · VQFN-24-EP(4x4)

SN65LVPE502ARGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Positive supply voltage; must be 3.3 V ±10%
2 EQ1 input LVCMOS control input to select equalization settings for CH1; internally biased to VCC/2
3 DE1 input LVCMOS control input to select de-emphasis settings for CH1; internally biased to VCC/2
4 OS1 input LVCMOS control input to select output amplitude for CH1; internally biased to VCC/2
5 EN_RXD input LVCMOS control input to set device operation modes; internally pulled to VCC
6 GND power_in Supply ground
7 NC unconnected Not internally connected
8 Host_RX1- input CML inverting differential input for CH1 with internal voltage bias and dual termination resistor circuit; must connect to USB 3.0 host side
9 Host_RX1+ input CML noninverting differential input for CH1 with internal voltage bias and dual termination resistor circuit; must connect to USB 3.0 host side
10 GND power_in Supply ground
11 Host_TX2- output CML inverting differential output for CH2 with internal voltage bias and termination resistor circuit; must connect to USB 3.0 host side
12 Host_TX2+ output CML noninverting differential output for CH2 with internal voltage bias and termination resistor circuit; must connect to USB 3.0 host side
13 VCC power_in Positive supply voltage; must be 3.3 V ±10%
14 RSVD input Reserved LVCMOS input; can be left as no-connect
15 OS2 input LVCMOS control input to select output amplitude for CH2; internally biased to VCC/2
16 DE2 input LVCMOS control input to select de-emphasis settings for CH2; internally biased to VCC/2
17 EQ2 input LVCMOS control input to select equalization settings for CH2; internally biased to VCC/2
18 GND power_in Supply ground
19 Device_RX2+ input CML noninverting differential input for CH2 with internal voltage bias and dual termination resistor circuit; must connect to USB 3.0 device side
20 Device_RX2- input CML inverting differential input for CH2 with internal voltage bias and dual termination resistor circuit; must connect to USB 3.0 device side
21 GND power_in Supply ground
22 Device_TX1+ output CML noninverting differential output for CH1 with internal voltage bias and termination resistor circuit; must connect to USB 3.0 device side
23 Device_TX1- output CML inverting differential output for CH1 with internal voltage bias and termination resistor circuit; must connect to USB 3.0 device side
24 NC unconnected Not internally connected
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Interface
Pins 25

CAD (KiCad official)

  • Symbol: SN65LVPE502ARGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: sn65lvpe502arger-etched.step / sn65lvpe502arger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65lvpe502arger.step / sn65lvpe502arger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (36 pp, sha256 a087ec23ade77dcf, retrieved 2026-10-03, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF