component
SN65LVPE502ARGER
Public Made by Adomby adom
Texas Instruments USB Converters, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+62@@ -0,0 +1,62 @@+# SN65LVPE502ARGER++**Texas Instruments** · USB Converters · VQFN-24-EP(4x4)++SN65LVPE502ARGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VCC | power_in | Positive supply voltage; must be 3.3 V ±10% |+| 2 | EQ1 | input | LVCMOS control input to select equalization settings for CH1; internally biased to VCC/2 |+| 3 | DE1 | input | LVCMOS control input to select de-emphasis settings for CH1; internally biased to VCC/2 |+| 4 | OS1 | input | LVCMOS control input to select output amplitude for CH1; internally biased to VCC/2 |+| 5 | EN_RXD | input | LVCMOS control input to set device operation modes; internally pulled to VCC |+| 6 | GND | power_in | Supply ground |+| 7 | NC | unconnected | Not internally connected |+| 8 | Host_RX1- | input | CML inverting differential input for CH1 with internal voltage bias and dual termination resistor circuit; must connect to USB 3.0 host side |+| 9 | Host_RX1+ | input | CML noninverting differential input for CH1 with internal voltage bias and dual termination resistor circuit; must connect to USB 3.0 host side |+| 10 | GND | power_in | Supply ground |+| 11 | Host_TX2- | output | CML inverting differential output for CH2 with internal voltage bias and termination resistor circuit; must connect to USB 3.0 host side |+| 12 | Host_TX2+ | output | CML noninverting differential output for CH2 with internal voltage bias and termination resistor circuit; must connect to USB 3.0 host side |+| 13 | VCC | power_in | Positive supply voltage; must be 3.3 V ±10% |+| 14 | RSVD | input | Reserved LVCMOS input; can be left as no-connect |+| 15 | OS2 | input | LVCMOS control input to select output amplitude for CH2; internally biased to VCC/2 |+| 16 | DE2 | input | LVCMOS control input to select de-emphasis settings for CH2; internally biased to VCC/2 |+| 17 | EQ2 | input | LVCMOS control input to select equalization settings for CH2; internally biased to VCC/2 |+| 18 | GND | power_in | Supply ground |+| 19 | Device_RX2+ | input | CML noninverting differential input for CH2 with internal voltage bias and dual termination resistor circuit; must connect to USB 3.0 device side |+| 20 | Device_RX2- | input | CML inverting differential input for CH2 with internal voltage bias and dual termination resistor circuit; must connect to USB 3.0 device side |+| 21 | GND | power_in | Supply ground |+| 22 | Device_TX1+ | output | CML noninverting differential output for CH1 with internal voltage bias and termination resistor circuit; must connect to USB 3.0 device side |+| 23 | Device_TX1- | output | CML inverting differential output for CH1 with internal voltage bias and termination resistor circuit; must connect to USB 3.0 device side |+| 24 | NC | unconnected | Not internally connected |+| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-24-EP(4x4) |+| Category | Interface |+| Pins | 25 |++## CAD (KiCad official)++- Symbol: `SN65LVPE502ARGER`+- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`+- 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)+- 3D model files: `sn65lvpe502arger-etched.step` / `sn65lvpe502arger-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn65lvpe502arger.step` / `sn65lvpe502arger.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn65lvpe502a) (36 pp, sha256 `a087ec23ade77dcf`, retrieved 2026-10-03, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn65lvpe502arger-datasheet.pdf)
page.jsonadded+264@@ -0,0 +1,264 @@+{+ "slug": "sn65lvpe502arger",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments USB Converters, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "sn65lvpe502arger",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn65lvpe502arger.kicad_sym",+ "sn65lvpe502arger.kicad_mod",+ "sn65lvpe502arger.glb",+ "sn65lvpe502arger.step",+ "sn65lvpe502arger.lbr",+ "docs/hero.png",+ "docs/sn65lvpe502arger-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn65lvpe502arger-hero.glb",+ "sn65lvpe502arger-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN65LVPE502ARGER",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-24-EP(4x4)",+ "pin_count": 25,+ "category": "Interface",+ "subcategory": "USB Converters",+ "datasheet": "https://www.ti.com/cn/lit/gpn/sn65lvpe502a",+ "parts": {+ "symbol": "sn65lvpe502arger.kicad_sym",+ "footprint": "sn65lvpe502arger.kicad_mod",+ "model_3d": "sn65lvpe502arger-hero.glb",+ "model_3d_plain": "sn65lvpe502arger.glb",+ "model_3d_step": "sn65lvpe502arger-etched.step",+ "model_3d_step_plain": "sn65lvpe502arger.step",+ "lbr": "sn65lvpe502arger.lbr"+ },+ "distributor_links": {+ "lcsc": 122835,+ "digikey": "296-35743-2-ND",+ "mouser": "595-SN65LVPE502ARGER"+ },+ "distributor_check": {+ "checked_at": "2026-10-03T08:15:20Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-35743-2-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-SN65LVPE502ARGER",+ "status": "found",+ "lifecycle": "Not Recommended for New Designs"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage; must be 3.3 V ±10%"+ },+ {+ "number": "2",+ "name": "EQ1",+ "type": "input",+ "description": "LVCMOS control input to select equalization settings for CH1; internally biased to VCC/2"+ },+ {+ "number": "3",+ "name": "DE1",+ "type": "input",+ "description": "LVCMOS control input to select de-emphasis settings for CH1; internally biased to VCC/2"+ },+ {+ "number": "4",+ "name": "OS1",+ "type": "input",+ "description": "LVCMOS control input to select output amplitude for CH1; internally biased to VCC/2"+ },+ {+ "number": "5",+ "name": "EN_RXD",+ "type": "input",+ "description": "LVCMOS control input to set device operation modes; internally pulled to VCC"+ },+ {+ "number": "6",+ "name": "GND",+ "type": "power_in",+ "description": "Supply ground"+ },+ {+ "number": "7",+ "name": "NC",+ "type": "unconnected",+ "description": "Not internally connected"+ },+ {+ "number": "8",+ "name": "Host_RX1–",+ "type": "input",+ "description": "CML inverting differential input for CH1 with internal voltage bias and dual termination resistor circuit; must connect to USB 3.0 host side"+ },+ {+ "number": "9",+ "name": "Host_RX1+",+ "type": "input",+ "description": "CML noninverting differential input for CH1 with internal voltage bias and dual termination resistor circuit; must connect to USB 3.0 host side"+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Supply ground"+ },+ {+ "number": "11",+ "name": "Host_TX2–",+ "type": "output",+ "description": "CML inverting differential output for CH2 with internal voltage bias and termination resistor circuit; must connect to USB 3.0 host side"+ },+ {+ "number": "12",+ "name": "Host_TX2+",+ "type": "output",+ "description": "CML noninverting differential output for CH2 with internal voltage bias and termination resistor circuit; must connect to USB 3.0 host side"+ },+ {+ "number": "13",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage; must be 3.3 V ±10%"+ },+ {+ "number": "14",+ "name": "RSVD",+ "type": "input",+ "description": "Reserved LVCMOS input; can be left as no-connect"+ },+ {+ "number": "15",+ "name": "OS2",+ "type": "input",+ "description": "LVCMOS control input to select output amplitude for CH2; internally biased to VCC/2"+ },+ {+ "number": "16",+ "name": "DE2",+ "type": "input",+ "description": "LVCMOS control input to select de-emphasis settings for CH2; internally biased to VCC/2"+ },+ {+ "number": "17",+ "name": "EQ2",+ "type": "input",+ "description": "LVCMOS control input to select equalization settings for CH2; internally biased to VCC/2"+ },+ {+ "number": "18",+ "name": "GND",+ "type": "power_in",+ "description": "Supply ground"+ },+ {+ "number": "19",+ "name": "Device_RX2+",+ "type": "input",+ "description": "CML noninverting differential input for CH2 with internal voltage bias and dual termination resistor circuit; must connect to USB 3.0 device side"+ },+ {+ "number": "20",+ "name": "Device_RX2–",+ "type": "input",+ "description": "CML inverting differential input for CH2 with internal voltage bias and dual termination resistor circuit; must connect to USB 3.0 device side"+ },+ {+ "number": "21",+ "name": "GND",+ "type": "power_in",+ "description": "Supply ground"+ },+ {+ "number": "22",+ "name": "Device_TX1+",+ "type": "output",+ "description": "CML noninverting differential output for CH1 with internal voltage bias and termination resistor circuit; must connect to USB 3.0 device side"+ },+ {+ "number": "23",+ "name": "Device_TX1–",+ "type": "output",+ "description": "CML inverting differential output for CH1 with internal voltage bias and termination resistor circuit; must connect to USB 3.0 device side"+ },+ {+ "number": "24",+ "name": "NC",+ "type": "unconnected",+ "description": "Not internally connected"+ },+ {+ "number": "25",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Per design note (3) on page 4, for SN65LVPE502A, TI recommends that at least two of the four pins (6",+ "exposed pad 25 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 9,+ "cost_usd": 0.1617,+ "at": "2026-10-03T08:14:57"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn65lvpe502a",+ "pages": 36,+ "sha256": "a087ec23ade77dcf",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 25,+ "described": 25,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}