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SN65LVEL11DR

Texas Instruments · Clock Buffers, Drivers, Distributors · SOIC-8

SN65LVEL11DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q0 output True PECL/ECL output of channel 0 of the 1:2 fanout buffer.
2 Q0̅ output Complementary PECL/ECL output of channel 0 of the 1:2 fanout buffer.
3 Q1 output True PECL/ECL output of channel 1 of the 1:2 fanout buffer.
4 Q1̅ output Complementary PECL/ECL output of channel 1 of the 1:2 fanout buffer.
5 VEE power_in Negative supply; 0 V in PECL mode, or -3.0 V to -3.8 V in NECL mode.
6 D̅ input Complementary PECL/ECL data input with a built-in 75 kΩ internal pull-down resistor.
7 D input True PECL/ECL data input with a built-in 75 kΩ internal pull-down resistor.
8 VCC power_in Positive supply; 3.0 V to 3.8 V in PECL mode, or 0 V in NECL mode.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Clock/Timing
Pins 8

CAD (KiCad official)

  • Symbol: SN65LVEL11DR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: sn65lvel11dr-etched.step / sn65lvel11dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65lvel11dr.step / sn65lvel11dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (18 pp, sha256 9a00c70dae66e127, retrieved 2026-10-08, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF