component
SN65LVDT41PW
Public Made by Adomby adom
Texas Instruments LVDS ICs, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownSN65LVDT41PW
Texas Instruments · LVDS ICs · TSSOP-20
SN65LVDT41PW from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1D | input | LVTTL driver input pin for channel 1, with VIH of at least 2 V and VIL of at most 0.8 V. |
| 2 | GND | power_in | Ground pin. |
| 3 | 2D | input | LVTTL driver input pin for channel 2, with VIH of at least 2 V and VIL of at most 0.8 V. |
| 4 | VCC | power_in | Power supply pin, +3.3 V ± 0.3 V (3 V to 3.6 V recommended operating range). |
| 5 | 3D | input | LVTTL driver input pin for channel 3, with VIH of at least 2 V and VIL of at most 0.8 V. |
| 6 | GND | power_in | Ground pin. |
| 7 | 4D | input | LVTTL driver input pin for channel 4, with VIH of at least 2 V and VIL of at most 0.8 V. |
| 8 | VCC | power_in | Power supply pin, +3.3 V ± 0.3 V (3 V to 3.6 V recommended operating range). |
| 9 | 5R | output | LVTTL receiver output pin for the single receiver channel. |
| 10 | GND | power_in | Ground pin. |
| 11 | 5B | input | Inverting LVDS receiver input pin; differential input magnitude |
| 12 | 5A | input | Noninverting LVDS receiver input pin; differential input magnitude |
| 13 | 4Z | output | Inverting LVDS driver output pin for channel 4. |
| 14 | 4Y | output | Noninverting LVDS driver output pin for channel 4. |
| 15 | 3Z | output | Inverting LVDS driver output pin for channel 3. |
| 16 | 3Y | output | Noninverting LVDS driver output pin for channel 3. |
| 17 | 2Z | output | Inverting LVDS driver output pin for channel 2. |
| 18 | 2Y | output | Noninverting LVDS driver output pin for channel 2. |
| 19 | 1Z | output | Inverting LVDS driver output pin for channel 1. |
| 20 | 1Y | output | Noninverting LVDS driver output pin for channel 1. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Interface |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
SN65LVDT41PW - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
sn65lvdt41pw-etched.step/sn65lvdt41pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn65lvdt41pw.step/sn65lvdt41pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (36 pp, sha256
03c706fa7aacda22, retrieved 2026-10-08, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).