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SN65LVDT348PWR

Public Made by Adom

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Texas Instruments Pre-ordered Chips, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN65LVDT348PWR

Texas Instruments · Pre-ordered Chips · TSSOP-16

SN65LVDT348PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RIN1- input Receiver 1 inverting differential input, with -4 V to 5 V common-mode range and an integrated 110-Ω termination to RIN1+ on the LVDT348.
2 RIN1+ input Receiver 1 non-inverting differential input, with -4 V to 5 V common-mode range and an integrated 110-Ω termination to RIN1- on the LVDT348.
3 RIN2+ input Receiver 2 non-inverting differential input, with -4 V to 5 V common-mode range and an integrated 110-Ω termination to RIN2- on the LVDT348.
4 RIN2- input Receiver 2 inverting differential input, with -4 V to 5 V common-mode range and an integrated 110-Ω termination to RIN2+ on the LVDT348.
5 RIN3- input Receiver 3 inverting differential input, with -4 V to 5 V common-mode range and an integrated 110-Ω termination to RIN3+ on the LVDT348.
6 RIN3+ input Receiver 3 non-inverting differential input, with -4 V to 5 V common-mode range and an integrated 110-Ω termination to RIN3- on the LVDT348.
7 RIN4+ input Receiver 4 non-inverting differential input, with -4 V to 5 V common-mode range and an integrated 110-Ω termination to RIN4- on the LVDT348.
8 RIN4- input Receiver 4 inverting differential input, with -4 V to 5 V common-mode range and an integrated 110-Ω termination to RIN4+ on the LVDT348.
9 EN input Complementary (active-low) enable input shared by all four receivers: outputs are enabled when it is low or open (with the other enable high) and high-impedance when it is high, with VIH of 2 V to 5 V and VIL of 0 V to 0.8 V.
10 ROUT4 tri_state Receiver 4 LVTTL output, high-impedance when disabled, with VOH of at least 2.4 V at -4 mA and VOL of at most 0.4 V at 4 mA.
11 ROUT3 tri_state Receiver 3 LVTTL output, high-impedance when disabled, with VOH of at least 2.4 V at -4 mA and VOL of at most 0.4 V at 4 mA.
12 GND power_in Ground pin for the device, the reference for all voltages except differential I/O bus voltages.
13 VCC power_in Supply voltage input, 3 V to 3.6 V (3.3 V nominal), absolute maximum -0.5 V to 4 V.
14 ROUT2 tri_state Receiver 2 LVTTL output, high-impedance when disabled, with VOH of at least 2.4 V at -4 mA and VOL of at most 0.4 V at 4 mA.
15 ROUT1 tri_state Receiver 1 LVTTL output, high-impedance when disabled, with VOH of at least 2.4 V at -4 mA and VOL of at most 0.4 V at 4 mA.
16 EN input Active-high enable input shared by all four receivers: outputs are enabled when it is high (with the other enable low or open) and high-impedance when it is low, with VIH of 2 V to 5 V and VIL of 0 V to 0.8 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Interface ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Differential input resistance RT 90 111 132 Ω VCC = 0 V, VID = 250 mV, VI = 0 V or 2.4 V 6
Positive-going differential input voltage threshold VITH1 50 mV See Figure 1 and Figure 2 6
Negative-going differential input voltage threshold VITH2 -50 mV See Figure 1 and Figure 2 6
Differential input failsafe voltage threshold VITH3 -100 -32 mV See Figure 1 and Table 1 6
Differential input voltage hysteresis VID(HYS) 50 mV VITH1 - VITH2 6
High-level output voltage VOH 2.4 V IOH = -4 mA 6
Low-level output voltage VOL 0.4 V IOL = 4 mA 6
Supply current, enabled ICC 16 20 mA LVDT348, Enabled, EN at VCC, EN at 0 V, No load 6
Supply current, disabled ICC 1.1 4 mA LVDT348, Disabled, EN at 0 or EN at VCC 6
Input current II -150 0 µA LVDT348, VI = -4 V, Other input open 6
Input current II -40 0 µA LVDT348, 0 V ≤ VI ≤ 2.4 V, Other input open 6
Input current II 0 80 µA LVDT348, VI = 5 V, Other input open 6
Power-off input current II(OFF) -100 100 µA LVDT348, VCC = 1.5 V, VI = -4 V or 5 V, Other input open 6
Power-off input current II(OFF) -40 40 µA LVDT348, VCC = 1.5 V, VI = 0 V or 2.4 V, Other input open 6
High-level input current, enables IIH 0 10 µA VIH = 2 V 6
Low-level input current, enables IIL 0 10 µA VIL = 0.8 V 6
High-impedance output current IOZ -10 10 µA VO = 0 V 6
Input capacitance CIN 5 pF VI = 0.4 sin (4E6πft) + 0.5 V 6
Propagation delay time, low-to-high-level output tPLH 2.5 4 6 ns CL = 10 pF, See Figure 3 7
Propagation delay time, high-to-low-level output tPHL 2.5 4 6 ns CL = 10 pF, See Figure 3 7
Delay time, failsafe disable time td1 12 ns 7
Delay time, failsafe enable time td2 0.3 1.5 µs 7
Pulse skew tsk(p) 200 ps CL = 10 pF, See Figure 3 7
Output skew tsk(o) 150 ps CL = 10 pF, See Figure 3 7
Part-to-part skew tsk(pp) 1 ns CL = 10 pF, See Figure 3 7
Output signal rise time tr 1.2 ns CL = 10 pF, See Figure 3 7
Output signal fall time tf 1 ns CL = 10 pF, See Figure 3 7
Output signal rise time tr 650 ps CL = 1 pF, See Figure 3 7
Output signal fall time tf 400 ps CL = 1 pF, See Figure 3 7
Propagation delay time, high-level-to-high-impedance output tPHZ 5 9 ns See Figure 4 and Figure 5 7
Propagation delay time, low-level-to-high-impedance output tPLZ 5 9 ns See Figure 4 and Figure 5 7
Propagation delay time, high-impedance-to-high-level output tPZH 8 12 ns See Figure 4 and Figure 5 7
Propagation delay time, high-impedance-to-low-level output tPZL 8 12 ns See Figure 4 and Figure 5 7
Supply voltage VCC 3 3.3 3.6 V VCC, VCCA, VCCD1, VCCD2 5
High-level input voltage, enables VIH 2 5 V Enables 5
Low-level input voltage, enables VIL 0 0.8 V Enables 5
Magnitude of differential input voltage /VID/ 0.1 0.8 V LVDT348, 352 5
Input voltage -4 5 V Any combination of common mode or input signals 5
Operating free-air temperature TA -40 85 °C 5
Supply voltage range VCC -0.5 4 V VCC, VCCA, VCCD1, VCCD2 5
Voltage range, enables, ROUT, or Y -0.5 6 V 5
Differential input magnitude MVIDM 1 V LVDT only 5
Voltage range, RIN+, RIN-, A or B -5 6 V 5
ESD, human body model -15 15 kV A, B, RIN+, RIN- and GND 5
ESD, human body model -7 7 kV All pins 5
ESD, charged-device model -500 500 V All pins 5
Storage temperature range -65 150 °C 5
Power rating, PW16 774 mW TA ≤ 25°C 5
Operating factor above TA = 25°C, PW16 6.2 mW/°C PW16 5
Power rating, PW16 402 mW TA = 85°C 5

CAD (KiCad official)

  • Symbol: SN65LVDT348PWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: sn65lvdt348pwr-etched.step / sn65lvdt348pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65lvdt348pwr.step / sn65lvdt348pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 2c0dc95fd55420c0, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF