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SN65LVDT100DGKR

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Texas Instruments LVDS ICs, VSSOP-8-0.65mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN65LVDT100DGKR

Texas Instruments · LVDS ICs · VSSOP-8-0.65mm

SN65LVDT100DGKR from Texas Instruments, in a VSSOP-8-0.65mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected Not connected; the pin table lists pin 1 as NC for the SN65LVDT100.
2 A input Differential non-inverting input that accepts LVDS, LVPECL or CML signals over a 0-V to 4-V input voltage range.
3 B input Differential inverting input that accepts LVDS, LVPECL or CML signals over a 0-V to 4-V input voltage range.
4 NC unconnected Not connected; on the SN65LVDT100 this pin has no VBB function and should be left unconnected.
5 GND power_in Ground reference for the device.
6 Z output Differential inverting output with LVDS levels per TIA/EIA-644-A; the LVDT100 integrates a 110-Ω differential termination resistor.
7 Y output Differential non-inverting output with LVDS levels per TIA/EIA-644-A, driving nominally 100-Ω differential lines.
8 VCC power_in Supply voltage of 3.0 V to 3.6 V with 3.3 V nominal.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VSSOP-8-0.65mm
Category Communication Interface Chip/UART/485/232
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 3 3.3 3.6 V 4
Magnitude of differential input voltage (LVDT100) /VID/ 0.1 0.8 V 'LVDT100 or 'LVDT101 4
Input voltage (any combination of common-mode or input signals) VI 0 4 V 4
Operating free-air temperature TA -40 85 °C 4
Supply voltage range VCC -0.5 4 V 4
Voltage range (A, B, Y, Z) VI 0 4.3 V 4
Differential voltage /VA, VB/ VID 1 V 'LVDT100 and 'LVDT101 only 4
Junction-to-ambient thermal resistance (DGK) RθJA 263 °C/W DGK 8-pin package 5
Power dissipation rating (DGK) 377 mW TA ≤ 25°C 5
Power dissipation rating (DGK) 481 mW TA ≤ 85°C 5
Supply current, 'LVDx100 ICC 25 30 mA No load or input 5
Device power dissipation, 'LVDx100 PD 110 mW RL = 100 Ω, No input; Y and Z to VCC, 2 V through 50 Ω 5
Positive-going differential input voltage threshold (LVDT) VIT+ 100 mV See Figure 30 and Table 1 5
Negative-going differential input voltage threshold (LVDT) VIT- -100 mV See Figure 30 and Table 1 5
Input current (LVDT) II -40 40 µA VI = 0 V or 2.4 V, Other input open 5
Input current (LVDT) II 66 µA VI = 4 V, Other input open 5
Power off input current (LVDT) II(OFF) -40 40 µA VCC = 1.5 V, VI = 0 V or 2.4 V, Other input open 5
Power off input current (LVDT) II(OFF) 66 µA VCC = 1.5 V, VI = 4 V, Other input open 5
Differential input resistance R(T) 90 110 132 Ω VID = 300 mV or 500 mV, VIC = 0 V or 2.4 V 5
Differential output voltage magnitude (LVDS100/LVDT100) /VOD/ 247 340 454 mV 6
Change in differential output voltage magnitude between logic states Δ/VOD/ -50 50 mV See Figure 31 6
Steady-state common-mode output voltage VOC(SS) 1.125 1.375 V 6
Change in steady-state common-mode output voltage between logic states ΔVOC(SS) -50 50 mV See Figure 32 6
Peak-to-peak common-mode output voltage VOC(PP) 50 150 mV 6
Short-circuit output current IOS -24 24 mA VO(Y) or VO(Z) = 0 V 6
Differential short-circuit output current IOS(D) -12 12 mA VOD = 0 V 6
Propagation delay time, low-to-high-level output ('LVDx100) tPLH 300 470 800 ps 6
Propagation delay time, high-to-low-level output ('LVDx100) tPHL 300 470 800 ps 6
Part-to-part skew tsk(pp) 100 ps VID = 0.2 V, See Figure 33 6
Pulse skew (/tPHL, tPLH/) tsk(p) 5 50 ps 6
RMS period jitter tjit(per) 1 3.7 ps 1 GHz 50% duty-cycle square-wave input 6
Peak cycle-to-cycle jitter tjit(cc) 6 23 ps VID = 200 mV, VIC = 1.2 V, See Figure 34 6
Peak-to-peak jitter tjit(pp) 28 65 ps 2 GHz PRBS, 2^23, 1 run length, VID = 200 mV, VIC = 1.2 V, See Figure 34 6
Peak-to-peak deterministic jitter tjit(det) 17 48 ps 2 GHz PRBS, 2^7, 1 run length, VID = 200 mV, VIC = 1.2 V, See Figure 34 6

CAD (KiCad official)

  • Symbol: SN65LVDT100DGKR
  • Footprint: Package_SO:VSSOP-8_2.3x2mm_P0.5mm
  • 3D model: VSSOP-8-0.65mm (KiCad packages3D, STEP)
  • 3D model files: sn65lvdt100dgkr-etched.step / sn65lvdt100dgkr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65lvdt100dgkr.step / sn65lvdt100dgkr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (46 pp, sha256 668dcd080c86a87d, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF